*/
machine(L1Cache, "MI Example L1 Cache")
-: Sequencer * sequencer,
- CacheMemory * cacheMemory,
- int cache_response_latency = 12,
- int issue_latency = 2,
- bool send_evictions
+ : Sequencer * sequencer;
+ CacheMemory * cacheMemory;
+ Cycles cache_response_latency := 12;
+ Cycles issue_latency := 2;
+ bool send_evictions;
+
+ // NETWORK BUFFERS
+ MessageBuffer * requestFromCache, network="To", virtual_network="2",
+ ordered="true", vnet_type="request";
+ MessageBuffer * responseFromCache, network="To", virtual_network="4",
+ ordered="true", vnet_type="response";
+
+ MessageBuffer * forwardToCache, network="From", virtual_network="3",
+ ordered="true", vnet_type="forward";
+ MessageBuffer * responseToCache, network="From", virtual_network="4",
+ ordered="true", vnet_type="response";
{
-
- // NETWORK BUFFERS
- MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="true", vnet_type="request";
- MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="true", vnet_type="response";
-
- MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="true", vnet_type="forward";
- MessageBuffer responseToCache, network="From", virtual_network="4", ordered="true", vnet_type="response";
-
// STATES
state_declaration(State, desc="Cache states") {
I, AccessPermission:Invalid, desc="Not Present/Invalid";
// STRUCTURES
- TBETable TBEs, template_hack="<L1Cache_TBE>";
+ TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
// PROTOTYPES
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();
void set_tbe(TBE b);
void unset_tbe();
+ void profileMsgDelay(int virtualNetworkType, Cycles b);
Entry getCacheEntry(Address address), return_by_pointer="yes" {
return static_cast(Entry, "pointer", cacheMemory.lookup(address));
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {
- return getCacheEntry(addr).DataBlk;
- }
-
- GenericMachineType getNondirectHitMachType(MachineID sender) {
- if (machineIDToMachineType(sender) == MachineType:L1Cache) {
- //
- // NOTE direct local hits should not call this
- //
- return GenericMachineType:L1Cache_wCC;
- } else {
- return ConvertMachToGenericMach(machineIDToMachineType(sender));
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
}
- }
+ return getCacheEntry(addr).DataBlk;
+ }
// NETWORK PORTS
in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
if (forwardRequestNetwork_in.isReady()) {
- peek(forwardRequestNetwork_in, RequestMsg, block_on="Address") {
+ peek(forwardRequestNetwork_in, RequestMsg, block_on="Addr") {
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := TBEs[in_msg.Address];
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := TBEs[in_msg.Addr];
if (in_msg.Type == CoherenceRequestType:GETX) {
- trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
}
else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
- trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe);
}
else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
- trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe);
}
else if (in_msg.Type == CoherenceRequestType:INV) {
- trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
}
else {
error("Unexpected message");
in_port(responseNetwork_in, ResponseMsg, responseToCache) {
if (responseNetwork_in.isReady()) {
- peek(responseNetwork_in, ResponseMsg, block_on="Address") {
+ peek(responseNetwork_in, ResponseMsg, block_on="Addr") {
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := TBEs[in_msg.Address];
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := TBEs[in_msg.Addr];
if (in_msg.Type == CoherenceResponseType:DATA) {
- trigger(Event:Data, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
}
else {
error("Unexpected message");
// ACTIONS
action(a_issueRequest, "a", desc="Issue a request") {
- enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
- out_msg.Address := address;
+ enqueue(requestNetwork_out, RequestMsg, issue_latency) {
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
out_msg.Destination.add(map_Address_to_Directory(address));
}
action(b_issuePUT, "b", desc="Issue a PUT request") {
- enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
+ enqueue(requestNetwork_out, RequestMsg, issue_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:PUTX;
out_msg.Requestor := machineID;
out_msg.Destination.add(map_Address_to_Directory(address));
action(e_sendData, "e", desc="Send data from cache to requestor") {
peek(forwardRequestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
peek(forwardRequestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
assert(is_valid(tbe));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
}
action(n_popResponseQueue, "n", desc="Pop the response queue") {
- profileMsgDelay(1, responseNetwork_in.dequeue_getDelayCycles());
+ profileMsgDelay(1, responseNetwork_in.dequeue());
}
action(o_popForwardedRequestQueue, "o", desc="Pop the forwarded request queue") {
- profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles());
+ profileMsgDelay(2, forwardRequestNetwork_in.dequeue());
}
- action(p_profileMiss, "p", desc="Profile cache miss") {
- peek(mandatoryQueue_in, RubyRequest) {
- cacheMemory.profileMiss(in_msg);
- }
+ action(p_profileMiss, "pi", desc="Profile cache miss") {
+ ++cacheMemory.demand_misses;
+ }
+
+ action(p_profileHit, "ph", desc="Profile cache miss") {
+ ++cacheMemory.demand_hits;
}
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
- sequencer.readCallback(address,
- GenericMachineType:L1Cache,
- cache_entry.DataBlk);
+ sequencer.readCallback(address, cache_entry.DataBlk, false);
}
action(rx_load_hit, "rx", desc="External load completed.") {
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
- sequencer.readCallback(address,
- getNondirectHitMachType(in_msg.Sender),
- cache_entry.DataBlk);
+ sequencer.readCallback(address, cache_entry.DataBlk, true,
+ machineIDToMachineType(in_msg.Sender));
}
}
action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
- sequencer.writeCallback(address,
- GenericMachineType:L1Cache,
- cache_entry.DataBlk);
+ sequencer.writeCallback(address, cache_entry.DataBlk, false);
}
action(sx_store_hit, "sx", desc="External store completed.") {
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
- sequencer.writeCallback(address,
- getNondirectHitMachType(in_msg.Sender),
- cache_entry.DataBlk);
+ sequencer.writeCallback(address, cache_entry.DataBlk, true,
+ machineIDToMachineType(in_msg.Sender));
}
}
// TRANSITIONS
- transition({IS, IM, MI, II}, {Load, Ifetch, Store, Replacement}) {
+ transition({IS, IM, MI, II, MII}, {Load, Ifetch, Store, Replacement}) {
z_stall;
}
transition(M, Store) {
s_store_hit;
+ p_profileHit;
m_popMandatoryQueue;
}
transition(M, {Load, Ifetch}) {
r_load_hit;
+ p_profileHit;
m_popMandatoryQueue;
}
projects / gem5.git / blobdiff