* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "Directory protocol")
+machine(MachineType:Directory, "Directory protocol")
: DirectoryMemory * directory;
Cycles directory_latency := 12;
Cycles to_memory_controller_latency := 1;
vnet_type="request";
MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
vnet_type="request";
+ MessageBuffer * responseFromMemory;
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_I") {
// TBE entries for DMA requests
structure(TBE, desc="TBE entries for outstanding DMA requests") {
- Address PhysicalAddress, desc="physical address";
+ Addr PhysicalAddress, desc="physical address";
State TBEState, desc="Transient State";
DataBlock DataBlk, desc="Data to be written (DMA write only)";
int Len, desc="...";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
// ** OBJECTS **
TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+ Tick clockEdge();
+ Cycles ticksToCycles(Tick t);
+ Tick cyclesToTicks(Cycles c);
void set_tbe(TBE b);
void unset_tbe();
- Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+ Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
- State getState(TBE tbe, Address addr) {
+ State getState(TBE tbe, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
} else if (directory.isPresent(addr)) {
}
}
- void setState(TBE tbe, Address addr, State state) {
+ void setState(TBE tbe, Addr addr, State state) {
if (is_valid(tbe)) {
tbe.TBEState := state;
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
return Directory_State_to_permission(tbe.TBEState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
if (directory.isPresent(addr)) {
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
}
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
return num_functional_writes;
}
- MessageBuffer responseFromMemory;
-
// ** OUT_PORTS **
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
// ** IN_PORTS **
in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
- if (dmaRequestQueue_in.isReady()) {
+ if (dmaRequestQueue_in.isReady(clockEdge())) {
peek(dmaRequestQueue_in, DMARequestMsg) {
TBE tbe := TBEs[in_msg.LineAddress];
if (in_msg.Type == DMARequestType:READ) {
}
in_port(requestQueue_in, RequestMsg, requestToDir) {
- if (requestQueue_in.isReady()) {
+ if (requestQueue_in.isReady(clockEdge())) {
peek(requestQueue_in, RequestMsg) {
- TBE tbe := TBEs[in_msg.Addr];
+ TBE tbe := TBEs[in_msg.addr];
if (in_msg.Type == CoherenceRequestType:GETS) {
- trigger(Event:GETS, in_msg.Addr, tbe);
+ trigger(Event:GETS, in_msg.addr, tbe);
} else if (in_msg.Type == CoherenceRequestType:GETX) {
- trigger(Event:GETX, in_msg.Addr, tbe);
+ trigger(Event:GETX, in_msg.addr, tbe);
} else if (in_msg.Type == CoherenceRequestType:PUTX) {
- if (getDirectoryEntry(in_msg.Addr).Owner.isElement(in_msg.Requestor)) {
- trigger(Event:PUTX, in_msg.Addr, tbe);
+ if (getDirectoryEntry(in_msg.addr).Owner.isElement(in_msg.Requestor)) {
+ trigger(Event:PUTX, in_msg.addr, tbe);
} else {
- trigger(Event:PUTX_NotOwner, in_msg.Addr, tbe);
+ trigger(Event:PUTX_NotOwner, in_msg.addr, tbe);
}
} else {
error("Invalid message");
//added by SS
// off-chip memory request/response is done
in_port(memQueue_in, MemoryMsg, responseFromMemory) {
- if (memQueue_in.isReady()) {
+ if (memQueue_in.isReady(clockEdge())) {
peek(memQueue_in, MemoryMsg) {
- TBE tbe := TBEs[in_msg.Addr];
+ TBE tbe := TBEs[in_msg.addr];
if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
- trigger(Event:Memory_Data, in_msg.Addr, tbe);
+ trigger(Event:Memory_Data, in_msg.addr, tbe);
} else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
- trigger(Event:Memory_Ack, in_msg.Addr, tbe);
+ trigger(Event:Memory_Ack, in_msg.addr, tbe);
} else {
DPRINTF(RubySlicc,"%s\n", in_msg.Type);
error("Invalid message");
action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
peek(requestQueue_in, RequestMsg) {
enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:WB_ACK;
out_msg.Requestor := in_msg.Requestor;
out_msg.Destination.add(in_msg.Requestor);
action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") {
peek(memQueue_in, MemoryMsg) {
enqueue(forwardNetwork_out, RequestMsg, 1) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:WB_ACK;
out_msg.Requestor := in_msg.OriginalRequestorMachId;
out_msg.Destination.add(in_msg.OriginalRequestorMachId);
action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
peek(requestQueue_in, RequestMsg) {
enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:WB_NACK;
out_msg.Requestor := in_msg.Requestor;
out_msg.Destination.add(in_msg.Requestor);
action(d_sendData, "d", desc="Send data to requestor") {
peek(memQueue_in, MemoryMsg) {
enqueue(responseNetwork_out, ResponseMsg, 1) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.OriginalRequestorMachId);
action(f_forwardRequest, "f", desc="Forward request to owner") {
peek(requestQueue_in, RequestMsg) {
APPEND_TRANSITION_COMMENT("Own: ");
- APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.Addr).Owner);
+ APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.addr).Owner);
APPEND_TRANSITION_COMMENT("Req: ");
APPEND_TRANSITION_COMMENT(in_msg.Requestor);
enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := in_msg.Type;
out_msg.Requestor := in_msg.Requestor;
- out_msg.Destination := getDirectoryEntry(in_msg.Addr).Owner;
+ out_msg.Destination := getDirectoryEntry(in_msg.addr).Owner;
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
}
action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
peek(dmaRequestQueue_in, DMARequestMsg) {
enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:INV;
out_msg.Requestor := machineID;
out_msg.Destination := getDirectoryEntry(in_msg.PhysicalAddress).Owner;
}
action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") {
- requestQueue_in.dequeue();
+ requestQueue_in.dequeue(clockEdge());
}
action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
- dmaRequestQueue_in.dequeue();
+ dmaRequestQueue_in.dequeue(clockEdge());
}
action(v_allocateTBE, "v", desc="Allocate TBE") {
}
action(z_recycleRequestQueue, "z", desc="recycle request queue") {
- requestQueue_in.recycle();
+ requestQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
}
action(y_recycleDMARequestQueue, "y", desc="recycle dma request queue") {
- dmaRequestQueue_in.recycle();
+ dmaRequestQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
}
}
action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
- memQueue_in.dequeue();
+ memQueue_in.dequeue(clockEdge());
}
// TRANSITIONS
transition(I, GETX, IM) {
//d_sendData;
+ v_allocateTBEFromRequestNet;
qf_queueMemoryFetchRequest;
e_ownerIsRequestor;
i_popIncomingRequestQueue;
transition(IM, Memory_Data, M) {
d_sendData;
//e_ownerIsRequestor;
+ w_deallocateTBE;
l_popMemQueue;
}