cpu: Add TraceCPU to playback elastic traces

[gem5.git] / src / mem / protocol / MOESI_CMP_token-dma.sm

diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index 98666998a31b377b91a8e97715308813967be340..efe3db3cd800086fc9422177b6ca9b626a4e3c9f 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -27,14 +27,18 @@
  */
 
 
-machine(DMA, "DMA Controller") 
-: DMASequencer * dma_sequencer,
-  int request_latency = 6
-{
+machine(DMA, "DMA Controller")
+    : DMASequencer * dma_sequencer;
+      Cycles request_latency := 6;
 
-  MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response", no_vector="true";
-  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
+      // Messsage Queues
+      MessageBuffer * responseFromDir, network="From", virtual_network="5",
+            vnet_type="response";
+      MessageBuffer * reqToDirectory, network="To", virtual_network="0",
+            vnet_type="request";
 
+      MessageBuffer * mandatoryQueue;
+{
   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
@@ -48,36 +52,37 @@ machine(DMA, "DMA Controller")
     Ack,          desc="DMA write to memory completed";
   }
 
-  structure(DMASequencer, external="yes") {
-    void ackCallback();
-    void dataCallback(DataBlock);
-  }
+  State cur_state;
 
-  MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  State cur_state, no_vector="true";
+  Tick clockEdge();
 
-  State getState(Address addr) {
+  State getState(Addr addr) {
     return cur_state;
   }
-  void setState(Address addr, State state) {
-  cur_state := state;
+
+  void setState(Addr addr, State state) {
+    cur_state := state;
   }
 
-  AccessPermission getAccessPermission(Address addr) {
+  AccessPermission getAccessPermission(Addr addr) {
     return AccessPermission:NotPresent;
   }
 
-  void setAccessPermission(Address addr, State state) {
+  void setAccessPermission(Addr addr, State state) {
+  }
+
+  void functionalRead(Addr addr, Packet *pkt) {
+    error("DMA does not support functional read.");
   }
 
-  DataBlock getDataBlock(Address addr), return_by_ref="yes" {
-    error("DMA Controller does not support getDataBlock function.\n");
+  int functionalWrite(Addr addr, Packet *pkt) {
+    error("DMA does not support functional write.");
   }
 
   out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
 
   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
-    if (dmaRequestQueue_in.isReady()) {
+    if (dmaRequestQueue_in.isReady(clockEdge())) {
       peek(dmaRequestQueue_in, SequencerMsg) {
         if (in_msg.Type == SequencerRequestType:LD ) {
           trigger(Event:ReadRequest, in_msg.LineAddress);
@@ -91,7 +96,7 @@ machine(DMA, "DMA Controller")
   }
 
   in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
-    if (dmaResponseQueue_in.isReady()) {
+    if (dmaResponseQueue_in.isReady(clockEdge())) {
       peek( dmaResponseQueue_in, DMAResponseMsg) {
         if (in_msg.Type == DMAResponseType:ACK) {
           trigger(Event:Ack, in_msg.LineAddress);
@@ -106,9 +111,9 @@ machine(DMA, "DMA Controller")
 
   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
     peek(dmaRequestQueue_in, SequencerMsg) {
-      enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
+      enqueue(reqToDirectory_out, DMARequestMsg, request_latency) {
         out_msg.PhysicalAddress := in_msg.PhysicalAddress;
-        out_msg.LineAddress := in_msg.LineAddress; 
+        out_msg.LineAddress := in_msg.LineAddress;
         out_msg.Type := DMARequestType:READ;
         out_msg.Requestor := machineID;
         out_msg.DataBlk := in_msg.DataBlk;
@@ -121,9 +126,9 @@ machine(DMA, "DMA Controller")
 
   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
     peek(dmaRequestQueue_in, SequencerMsg) {
-      enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
+      enqueue(reqToDirectory_out, DMARequestMsg, request_latency) {
           out_msg.PhysicalAddress := in_msg.PhysicalAddress;
-          out_msg.LineAddress := in_msg.LineAddress; 
+          out_msg.LineAddress := in_msg.LineAddress;
           out_msg.Type := DMARequestType:WRITE;
           out_msg.Requestor := machineID;
           out_msg.DataBlk := in_msg.DataBlk;
@@ -147,11 +152,11 @@ machine(DMA, "DMA Controller")
   }
 
   action(p_popRequestQueue, "p", desc="Pop request queue") {
-    dmaRequestQueue_in.dequeue();
+    dmaRequestQueue_in.dequeue(clockEdge());
   }
 
   action(p_popResponseQueue, "\p", desc="Pop request queue") {
-    dmaResponseQueue_in.dequeue();
+    dmaResponseQueue_in.dequeue(clockEdge());
   }
 
   transition(READY, ReadRequest, BUSY_RD) {