*/
-machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- int request_latency = 6
-{
+machine(DMA, "DMA Controller")
+ : DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
- MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", no_vector="true";
- MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
+ // Messsage Queues
+ MessageBuffer * responseFromDir, network="From", virtual_network="5",
+ vnet_type="response";
+ MessageBuffer * reqToDirectory, network="To", virtual_network="0",
+ vnet_type="request";
+ MessageBuffer * mandatoryQueue;
+{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
Ack, desc="DMA write to memory completed";
}
- structure(DMASequencer, external="yes") {
- void ackCallback();
- void dataCallback(DataBlock);
- }
+ State cur_state;
- MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- State cur_state, no_vector="true";
+ Tick clockEdge();
- State getState(Address addr) {
+ State getState(Addr addr) {
return cur_state;
}
- void setState(Address addr, State state) {
- cur_state := state;
+
+ void setState(Addr addr, State state) {
+ cur_state := state;
+ }
+
+ AccessPermission getAccessPermission(Addr addr) {
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Addr addr, State state) {
+ }
+
+ void functionalRead(Addr addr, Packet *pkt) {
+ error("DMA does not support functional read.");
+ }
+
+ int functionalWrite(Addr addr, Packet *pkt) {
+ error("DMA does not support functional write.");
}
out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
- if (dmaRequestQueue_in.isReady()) {
+ if (dmaRequestQueue_in.isReady(clockEdge())) {
peek(dmaRequestQueue_in, SequencerMsg) {
if (in_msg.Type == SequencerRequestType:LD ) {
trigger(Event:ReadRequest, in_msg.LineAddress);
}
in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
- if (dmaResponseQueue_in.isReady()) {
+ if (dmaResponseQueue_in.isReady(clockEdge())) {
peek( dmaResponseQueue_in, DMAResponseMsg) {
if (in_msg.Type == DMAResponseType:ACK) {
trigger(Event:Ack, in_msg.LineAddress);
action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
peek(dmaRequestQueue_in, SequencerMsg) {
- enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
+ enqueue(reqToDirectory_out, DMARequestMsg, request_latency) {
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
- out_msg.LineAddress := in_msg.LineAddress;
+ out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:READ;
out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;
action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
peek(dmaRequestQueue_in, SequencerMsg) {
- enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
+ enqueue(reqToDirectory_out, DMARequestMsg, request_latency) {
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
- out_msg.LineAddress := in_msg.LineAddress;
+ out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:WRITE;
out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;
}
action(p_popRequestQueue, "p", desc="Pop request queue") {
- dmaRequestQueue_in.dequeue();
+ dmaRequestQueue_in.dequeue(clockEdge());
}
action(p_popResponseQueue, "\p", desc="Pop request queue") {
- dmaResponseQueue_in.dequeue();
+ dmaResponseQueue_in.dequeue(clockEdge());
}
transition(READY, ReadRequest, BUSY_RD) {