ruby: replace Time with Cycles (final patch in the series)

[gem5.git] / src / mem / protocol / RubySlicc_Exports.sm

diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index b42f9c3a94bb6b1e08f9f6a627099737746b4d45..03641909576dd2dbdf0ce5a3811c8b4b8d67fe14 100644 (file)
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -27,24 +27,24 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/*
- * $Id$
- *
- */
-
-// defines
+// Declarations of external types that are common to all protocols
 external_type(int, primitive="yes", default="0");
 external_type(bool, primitive="yes", default="false");
 external_type(std::string, primitive="yes");
+external_type(uint32_t, primitive="yes");
 external_type(uint64, primitive="yes");
-external_type(Time, primitive="yes", default="0");
+external_type(PacketPtr, primitive="yes");
+external_type(Packet, primitive="yes");
 external_type(Address);
+external_type(Cycles, primitive="yes", default="Cycles(0)");
+
 structure(DataBlock, external = "yes", desc="..."){
   void clear();
   void copyPartial(DataBlock, int, int);
 }
 
-// Declarations of external types that are common to all protocols
+bool testAndRead(Address addr, DataBlock datablk, Packet *pkt);
+bool testAndWrite(Address addr, DataBlock datablk, Packet *pkt);
 
 // AccessPermission
 // The following five states define the access permission of all memory blocks.
@@ -265,6 +265,14 @@ structure(SequencerMsg, desc="...", interface="Message") {
   DataBlock DataBlk,         desc="Data";
   int Len,                   desc="size in bytes of access";
   PrefetchBit Prefetch,      desc="Is this a prefetch request";
+
+  bool functionalRead(Packet *pkt) {
+    return testAndRead(PhysicalAddress, DataBlk, pkt);
+  }
+
+  bool functionalWrite(Packet *pkt) {
+    return testAndWrite(PhysicalAddress, DataBlk, pkt);
+  }
 }
 
 // MaskPredictorType