-
/*
- * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
+ * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
Read_Only, desc="block is Read Only (modulo functional writes)";
Read_Write, desc="block is Read/Write";
+ // Possibly Invalid data
+ // The maybe stale permission indicates that accordingly to the protocol,
+ // there is no guarantee the block contains valid data. However, functional
+ // writes should update the block because a dataless PUT request may
+ // revalidate the block's data.
+ Maybe_Stale, desc="block can be stale or revalidated by a dataless PUT";
+ // In Broadcast/Snoop protocols, memory has no idea if it is exclusive owner
+ // or not of a block, making it hard to make the logic of having only one
+ // read_write block in the system impossible. This is to allow the memory to
+ // say, "I have the block" and for the RubyPort logic to know that this is a
+ // last-resort block if there are no writable copies in the caching hierarchy.
+ // This is not supposed to be used in directory or token protocols where
+ // memory/NB has an idea of what is going on in the whole system.
+ Backing_Store, desc="for memory in Broadcast/Snoop protocols";
+
// Invalid data
Invalid, desc="block is in an Invalid base state";
NotPresent, desc="block is NotPresent";
ProtocolStall, desc="Protocol specified stall";
}
-// CacheRequestType
-enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
- LD, desc="Load";
- ST, desc="Store";
- ATOMIC, desc="Atomic Load/Store";
- IFETCH, desc="Instruction fetch";
- IO, desc="I/O";
- REPLACEMENT, desc="Replacement";
- COMMIT, desc="Commit version";
- NULL, desc="Invalid request type";
+// RubyRequestType
+enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
+ LD, desc="Load";
+ ST, desc="Store";
+ ATOMIC, desc="Atomic Load/Store";
+ IFETCH, desc="Instruction fetch";
+ IO, desc="I/O";
+ REPLACEMENT, desc="Replacement";
+ Load_Linked, desc="";
+ Store_Conditional, desc="";
+ RMW_Read, desc="";
+ RMW_Write, desc="";
+ Locked_RMW_Read, desc="";
+ Locked_RMW_Write, desc="";
+ COMMIT, desc="Commit version";
+ NULL, desc="Invalid request type";
+ FLUSH, desc="Flush request type";
}
enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
+ Default, desc="Replace this with access_types passed to the DMA Ruby object";
LD, desc="Load";
ST, desc="Store";
NULL, desc="Invalid request type";
NULL, desc="null request type";
}
+enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
+ DataArrayRead, desc="Read access to the cache's data array";
+ DataArrayWrite, desc="Write access to the cache's data array";
+ TagArrayRead, desc="Read access to the cache's tag array";
+ TagArrayWrite, desc="Write access to the cache's tag array";
+}
+
+enumeration(CacheResourceType, desc="...", default="CacheResourceType_NULL") {
+ DataArray, desc="Access to the cache's data array";
+ TagArray, desc="Access to the cache's tag array";
+}
+
+enumeration(DirectoryRequestType, desc="...", default="DirectoryRequestType_NULL") {
+ Default, desc="Replace this with access_types passed to the Directory Ruby object";
+}
+
+enumeration(DMASequencerRequestType, desc="...", default="DMASequencerRequestType_NULL") {
+ Default, desc="Replace this with access_types passed to the DMA Ruby object";
+}
+
+enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestType_NULL") {
+ Default, desc="Replace this with access_types passed to the DMA Ruby object";
+}
+
enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
L1Cache, desc="L1 Cache Mach";
L2Cache, desc="L2 Cache Mach";
L3Cache, desc="L3 Cache Mach";
Directory, desc="Directory Mach";
+ DMA, desc="DMA Mach";
Collector, desc="Collector Mach";
L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
L2_HW, desc="This is a L2 hardware prefetch";
}
-// CacheMsg
-structure(CacheMsg, desc="...", interface="Message") {
- Address LineAddress, desc="Line address for this request";
- Address PhysicalAddress, desc="Physical address for this request";
- CacheRequestType Type, desc="Type of request (LD, ST, etc)";
- Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
- RubyAccessMode AccessMode, desc="user/supervisor access type";
- int Size, desc="size in bytes of access";
- PrefetchBit Prefetch, desc="Is this a prefetch request";
-}
-
// CacheMsg
structure(SequencerMsg, desc="...", interface="Message") {
Address LineAddress, desc="Line address for this request";
Both, desc="Both";
}
-// Network Topologies
-enumeration(TopologyType, desc="...") {
- CROSSBAR, desc="One node per chip, single switch crossbar";
- HIERARCHICAL_SWITCH, desc="One node per chip, totally ordered hierarchical tree switched network";
- TORUS_2D, desc="One node per chip, 2D torus";
- PT_TO_PT, desc="One node per chip, Point to Point Network";
- FILE_SPECIFIED, desc="described by the file NETWORK_FILE";
-}
-
-// DNUCA AllocationStrategy
-enumeration(AllocationStrategy, desc="...") {
- InMiddle, desc="";
- InInvCorners, desc="";
- InSharedSides, desc="";
- StaticDist, desc="";
- RandomBank, desc="";
- FrequencyBank, desc="";
- FrequencyBlock, desc="";
- LRUBlock, desc="";
-}
-
-// DNUCA SearchMechanism
-enumeration(SearchMechanism, desc="...") {
- Perfect, desc="";
- PartialTag, desc="";
- BloomFilter, desc="";
- Random, desc="";
- None, desc="";
-}
-
-// DNUCA link type
-enumeration(LinkType, desc="...") {
- RC_1500UM, desc="";
- RC_2500UM, desc="";
- TL_9000UM, desc="";
- TL_11000UM, desc="";
- TL_13000UM, desc="";
- NO_ENERGY, desc="";
- NULL, desc="";
-}
-
-// transient request type
-enumeration(TransientRequestType, desc="...", default="TransientRequestType_Undefined") {
- Undefined, desc="";
- OffChip, desc="";
- OnChip, desc="";
- LocalTransient, desc="";
-}
-
// Request Status
enumeration(RequestStatus, desc="...", default="RequestStatus_NULL") {
Ready, desc="The sequencer is ready and the request does not alias";
Aliased, desc="This request aliased with a currently outstanding request";
NULL, desc="";
}
+
+// LinkDirection
+enumeration(LinkDirection, desc="...") {
+ In, desc="Inward link direction";
+ Out, desc="Outward link direction";
+}
projects / gem5.git / blobdiff