/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "debug/Drain.hh"
#include "debug/QOS.hh"
#include "mem_sink.hh"
+#include "params/QoSMemSinkInterface.hh"
#include "sim/system.hh"
namespace QoS {
-MemSinkCtrl::MemSinkCtrl(const QoSMemSinkCtrlParams* p)
- : MemCtrl(p), requestLatency(p->request_latency),
- responseLatency(p->response_latency),
- memoryPacketSize(p->memory_packet_size),
- readBufferSize(p->read_buffer_size),
- writeBufferSize(p->write_buffer_size), port(name() + ".port", *this),
- retryRdReq(false), retryWrReq(false), nextRequest(0), nextReqEvent(this)
+MemSinkCtrl::MemSinkCtrl(const QoSMemSinkCtrlParams &p)
+ : MemCtrl(p), requestLatency(p.request_latency),
+ responseLatency(p.response_latency),
+ memoryPacketSize(p.memory_packet_size),
+ readBufferSize(p.read_buffer_size),
+ writeBufferSize(p.write_buffer_size), port(name() + ".port", *this),
+ interface(p.interface),
+ retryRdReq(false), retryWrReq(false), nextRequest(0), nextReqEvent(this),
+ stats(this)
{
// Resize read and write queue to allocate space
// for configured QoS priorities
readQueue.resize(numPriorities());
writeQueue.resize(numPriorities());
+
+ interface->setMemCtrl(this);
}
MemSinkCtrl::~MemSinkCtrl()
"%s Should not see packets where cache is responding\n",
__func__);
- access(pkt);
+ interface->access(pkt);
return responseLatency;
}
{
pkt->pushLabel(name());
- functionalAccess(pkt);
+ interface->functionalAccess(pkt);
pkt->popLabel();
}
-BaseSlavePort &
-MemSinkCtrl::getSlavePort(const std::string &interface, PortID idx)
+Port &
+MemSinkCtrl::getPort(const std::string &interface, PortID idx)
{
if (interface != "port") {
- return MemObject::getSlavePort(interface, idx);
+ return MemCtrl::getPort(interface, idx);
} else {
return port;
}
__func__);
DPRINTF(QOS,
- "%s: MASTER %s request %s addr %lld size %d\n",
+ "%s: REQUESTOR %s request %s addr %lld size %d\n",
__func__,
- _system->getMasterName(pkt->req->masterId()),
+ _system->getRequestorName(pkt->req->requestorId()),
pkt->cmdString(), pkt->getAddr(), pkt->getSize());
uint64_t required_entries = divCeil(pkt->getSize(), memoryPacketSize);
"%s Read queue full, not accepting\n", __func__);
// Remember that we have to retry this port
retryRdReq = true;
- numReadRetries++;
+ stats.numReadRetries++;
req_accepted = false;
} else {
// Enqueue the incoming packet into corresponding
"%s Write queue full, not accepting\n", __func__);
// Remember that we have to retry this port
retryWrReq = true;
- numWriteRetries++;
+ stats.numWriteRetries++;
req_accepted = false;
} else {
// Enqueue the incoming packet into corresponding QoS
if (req_accepted) {
// The packet is accepted - log it
logRequest(pkt->isRead()? READ : WRITE,
- pkt->req->masterId(),
+ pkt->req->requestorId(),
pkt->qosValue(),
pkt->getAddr(),
required_entries);
for (uint8_t i = 0; i < numPriorities(); ++i) {
std::string plist = "";
for (auto& e : (busState == WRITE ? writeQueue[i]: readQueue[i])) {
- plist += (std::to_string(e->req->masterId())) + " ";
+ plist += (std::to_string(e->req->requestorId())) + " ";
}
DPRINTF(QOS,
"%s priority Queue [%i] contains %i elements, "
queue->erase(p_it);
DPRINTF(QOS,
- "%s scheduling packet address %d for master %s from "
+ "%s scheduling packet address %d for requestor %s from "
"priority queue %d\n", __func__, pkt->getAddr(),
- _system->getMasterName(pkt->req->masterId()),
+ _system->getRequestorName(pkt->req->requestorId()),
curr_prio);
break;
}
uint64_t removed_entries = divCeil(pkt->getSize(), memoryPacketSize);
DPRINTF(QOS,
- "%s scheduled packet address %d for master %s size is %d, "
+ "%s scheduled packet address %d for requestor %s size is %d, "
"corresponds to %d memory packets\n", __func__, pkt->getAddr(),
- _system->getMasterName(pkt->req->masterId()),
+ _system->getRequestorName(pkt->req->requestorId()),
pkt->getSize(), removed_entries);
// Schedule response
// Do the actual memory access which also turns the packet
// into a response
- access(pkt);
+ interface->access(pkt);
// Log the response
logResponse(pkt->isRead()? READ : WRITE,
- pkt->req->masterId(),
+ pkt->req->requestorId(),
pkt->qosValue(),
pkt->getAddr(),
removed_entries, responseLatency);
// Schedule the response
- port.schedTimingResp(pkt, curTick() + responseLatency, true);
+ port.schedTimingResp(pkt, curTick() + responseLatency);
DPRINTF(QOS,
"%s response scheduled at time %d\n",
__func__, curTick() + responseLatency);
}
}
-void
-MemSinkCtrl::regStats()
+MemSinkCtrl::MemSinkCtrlStats::MemSinkCtrlStats(Stats::Group *parent)
+ : Stats::Group(parent),
+ ADD_STAT(numReadRetries, UNIT_COUNT, "Number of read retries"),
+ ADD_STAT(numWriteRetries, UNIT_COUNT, "Number of write retries")
{
- MemCtrl::regStats();
-
- // Initialize all the stats
- using namespace Stats;
-
- numReadRetries.name(name() + ".numReadRetries")
- .desc("Number of read retries");
- numWriteRetries.name(name() + ".numWriteRetries")
- .desc("Number of write retries");
}
MemSinkCtrl::MemoryPort::MemoryPort(const std::string& n,
MemSinkCtrl& m)
- : QueuedSlavePort(n, &m, queue), memory(m), queue(memory, *this)
+ : QueuedResponsePort(n, &m, queue, true),
+ memory(m), queue(memory, *this, true)
{}
AddrRangeList
MemSinkCtrl::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
- ranges.push_back(memory.getAddrRange());
+ ranges.push_back(memory.interface->getAddrRange());
return ranges;
}
} // namespace QoS
-QoS::MemSinkCtrl*
-QoSMemSinkCtrlParams::create()
+QoSMemSinkInterface::QoSMemSinkInterface(const QoSMemSinkInterfaceParams &_p)
+ : AbstractMemory(_p)
{
- return new QoS::MemSinkCtrl(this);
}
-
projects / gem5.git / blobdiff