/*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2013,2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include <climits>
#include "base/flags.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "sim/core.hh"
class Request
{
public:
- typedef uint32_t FlagsType;
+ typedef uint64_t FlagsType;
typedef uint8_t ArchFlagsType;
typedef ::Flags<FlagsType> Flags;
/** The request is a page table walk */
PT_WALK = 0x20000000,
+ /** The request invalidates a memory location */
+ INVALIDATE = 0x0000000100000000,
+ /** The request cleans a memory location */
+ CLEAN = 0x0000000200000000,
+
+ /** The request targets the point of unification */
+ DST_POU = 0x0000001000000000,
+
+ /** The request targets the point of coherence */
+ DST_POC = 0x0000002000000000,
+
+ /** Bits to define the destination of a request */
+ DST_BITS = 0x0000003000000000,
+
/**
* These flags are *not* cleared when a Request object is
* reused (assigned a new address).
*/
STICKY_FLAGS = INST_FETCH
};
+ static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
+ CLEAN | INVALIDATE;
/** Master Ids that are statically allocated
* @{*/
VALID_PC = 0x00000010,
/** Whether or not the context ID is valid. */
VALID_CONTEXT_ID = 0x00000020,
- VALID_THREAD_ID = 0x00000040,
/** Whether or not the sc result is valid. */
VALID_EXTRA_DATA = 0x00000080,
/**
* These flags are *not* cleared when a Request object is reused
* (assigned a new address).
*/
- STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID | VALID_THREAD_ID
+ STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
};
private:
* store conditional or the compare value for a CAS. */
uint64_t _extraData;
- /** The context ID (for statistics, typically). */
+ /** The context ID (for statistics, locks, and wakeups). */
ContextID _contextId;
- /** The thread ID (id within this CPU) */
- ThreadID _threadId;
/** program counter of initiating access; for tracing/debugging */
Addr _pc;
Request()
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{}
Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
- InstSeqNum seq_num, ContextID cid, ThreadID tid)
+ InstSeqNum seq_num, ContextID cid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
setPhys(paddr, size, flags, mid, curTick());
- setThreadContext(cid, tid);
+ setContext(cid);
privateFlags.set(VALID_INST_SEQ_NUM);
}
Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
Addr pc)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(pc),
+ _extraData(0), _contextId(0), _pc(pc),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
}
Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
- Addr pc, ContextID cid, ThreadID tid)
+ Addr pc, ContextID cid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
setVirt(asid, vaddr, size, flags, mid, pc);
- setThreadContext(cid, tid);
+ setContext(cid);
}
- Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
- int cid, ThreadID tid, AtomicOpFunctor *atomic_op)
+ Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
+ Addr pc, ContextID cid, AtomicOpFunctor *atomic_op)
: atomicOpFunctor(atomic_op)
{
setVirt(asid, vaddr, size, flags, mid, pc);
- setThreadContext(cid, tid);
+ setContext(cid);
}
~Request()
}
/**
- * Set up CPU and thread numbers.
+ * Set up Context numbers.
*/
void
- setThreadContext(ContextID context_id, ThreadID tid)
+ setContext(ContextID context_id)
{
_contextId = context_id;
- _threadId = tid;
- privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
+ privateFlags.set(VALID_CONTEXT_ID);
}
/**
return _contextId;
}
- /** Accessor function for thread ID. */
- ThreadID
- threadId() const
- {
- assert(privateFlags.isSet(VALID_THREAD_ID));
- return _threadId;
- }
-
void
setPC(Addr pc)
{
_flags.isSet(ATOMIC_NO_RETURN_OP);
}
+ /**
+ * Accessor functions for the destination of a memory request. The
+ * destination flag can specify a point of reference for the
+ * operation (e.g. a cache block clean to the the point of
+ * unification). At the moment the destination is only used by the
+ * cache maintenance operations.
+ */
+ bool isToPOU() const { return _flags.isSet(DST_POU); }
+ bool isToPOC() const { return _flags.isSet(DST_POC); }
+ Flags getDest() const { return _flags & DST_BITS; }
+
/**
* Accessor functions for the memory space configuration flags and used by
* GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
{
return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
}
+
+ /**
+ * Accessor functions to determine whether this request is part of
+ * a cache maintenance operation. At the moment three operations
+ * are supported:
+
+ * 1) A cache clean operation updates all copies of a memory
+ * location to the point of reference,
+ * 2) A cache invalidate operation invalidates all copies of the
+ * specified block in the memory above the point of reference,
+ * 3) A clean and invalidate operation is a combination of the two
+ * operations.
+ * @{ */
+ bool isCacheClean() const { return _flags.isSet(CLEAN); }
+ bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
+ bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
+ /** @} */
};
#endif // __MEM_REQUEST_HH__