*/
/**
- * @file Decleration of a request, the overall memory request consisting of
+ * @file
+ * Declaration of a request, the overall memory request consisting of
the parts of the request that are persistent throughout the transaction.
*/
#ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__
-#include "arch/isa_traits.hh"
+#include "base/fast_alloc.hh"
+#include "sim/host.hh"
+#include "sim/core.hh"
+
+#include <cassert>
class Request;
typedef Request* RequestPtr;
+
+/** ASI information for this request if it exsits. */
+const uint32_t ASI_BITS = 0x000FF;
/** The request is a Load locked/store conditional. */
-const unsigned LOCKED = 0x001;
+const uint32_t LOCKED = 0x00100;
/** The virtual address is also the physical address. */
-const unsigned PHYSICAL = 0x002;
+const uint32_t PHYSICAL = 0x00200;
/** The request is an ALPHA VPTE pal access (hw_ld). */
-const unsigned VPTE = 0x004;
+const uint32_t VPTE = 0x00400;
/** Use the alternate mode bits in ALPHA. */
-const unsigned ALTMODE = 0x008;
+const uint32_t ALTMODE = 0x00800;
/** The request is to an uncacheable address. */
-const unsigned UNCACHEABLE = 0x010;
+const uint32_t UNCACHEABLE = 0x01000;
/** The request should not cause a page fault. */
-const unsigned NO_FAULT = 0x020;
+const uint32_t NO_FAULT = 0x02000;
/** The request should be prefetched into the exclusive state. */
-const unsigned PF_EXCLUSIVE = 0x100;
+const uint32_t PF_EXCLUSIVE = 0x10000;
/** The request should be marked as LRU. */
-const unsigned EVICT_NEXT = 0x200;
+const uint32_t EVICT_NEXT = 0x20000;
+/** The request should ignore unaligned access faults */
+const uint32_t NO_ALIGN_FAULT = 0x40000;
+/** The request was an instruction read. */
+const uint32_t INST_READ = 0x80000;
+/** This request is for a memory swap. */
+const uint32_t MEM_SWAP = 0x100000;
+const uint32_t MEM_SWAP_COND = 0x200000;
/** The request should ignore unaligned access faults */
-const unsigned NO_ALIGN_FAULT = 0x400;
+const uint32_t NO_HALF_WORD_ALIGN_FAULT = 0x400000;
-class Request
+
+class Request : public FastAlloc
{
private:
/**
/** The address space ID. */
int asid;
+
+ /** This request is to a memory mapped register. */
+ bool mmapedIpr;
+
/** The virtual address of the request. */
Addr vaddr;
- /** The return value of store conditional. */
- uint64_t scResult;
+ /** Extra data for the request, such as the return value of
+ * store conditional or the compare value for a CAS. */
+ uint64_t extraData;
/** The cpu number (for statistics, typically). */
int cpuNum;
/** Whether or not the asid & vaddr are valid. */
bool validAsidVaddr;
/** Whether or not the sc result is valid. */
- bool validScResult;
+ bool validExData;
/** Whether or not the cpu number & thread ID are valid. */
bool validCpuAndThreadNums;
/** Whether or not the pc is valid. */
/** Minimal constructor. No fields are initialized. */
Request()
: validPaddr(false), validAsidVaddr(false),
- validScResult(false), validCpuAndThreadNums(false), validPC(false)
+ validExData(false), validCpuAndThreadNums(false), validPC(false)
{}
/**
setVirt(_asid, _vaddr, _size, _flags, _pc);
}
+ ~Request() {} // for FastAlloc
+
/**
* Set up CPU and thread numbers. */
void setThreadContext(int _cpuNum, int _threadNum)
validPaddr = true;
validAsidVaddr = false;
validPC = false;
- validScResult = false;
+ validExData = false;
+ mmapedIpr = false;
}
/**
validPaddr = false;
validAsidVaddr = true;
validPC = true;
- validScResult = false;
+ validExData = false;
+ mmapedIpr = false;
}
/** Set just the physical address. This should only be used to
int getSize() { assert(validPaddr || validAsidVaddr); return size; }
/** Accessor for time. */
Tick getTime() { assert(validPaddr || validAsidVaddr); return time; }
+ void resetTime() { assert(validPaddr || validAsidVaddr); time = curTick; }
/** Accessor for flags. */
uint32_t getFlags() { assert(validPaddr || validAsidVaddr); return flags; }
/** Accessor function for asid.*/
int getAsid() { assert(validAsidVaddr); return asid; }
+ /** Accessor function for asi.*/
+ uint8_t getAsi() { assert(validAsidVaddr); return flags & ASI_BITS; }
+
+ /** Accessor function for asi.*/
+ void setAsi(uint8_t a)
+ { assert(validAsidVaddr); flags = (flags & ~ASI_BITS) | a; }
+
+ /** Accessor function for asi.*/
+ bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; }
+
+ /** Accessor function for asi.*/
+ void setMmapedIpr(bool r) { assert(validAsidVaddr); mmapedIpr = r; }
+
+ /** Accessor function to check if sc result is valid. */
+ bool extraDataValid() { return validExData; }
/** Accessor function for store conditional return value.*/
- uint64_t getScResult() { assert(validScResult); return scResult; }
+ uint64_t getExtraData() { assert(validExData); return extraData; }
/** Accessor function for store conditional return value.*/
- void setScResult(uint64_t _scResult)
- { scResult = _scResult; validScResult = true; }
+ void setExtraData(uint64_t _extraData)
+ { extraData = _extraData; validExData = true; }
/** Accessor function for cpu number.*/
int getCpuNum() { assert(validCpuAndThreadNums); return cpuNum; }
/** Accessor function for pc.*/
Addr getPC() { assert(validPC); return pc; }
+ /** Accessor Function to Check Cacheability. */
+ bool isUncacheable() { return (getFlags() & UNCACHEABLE) != 0; }
+
+ bool isInstRead() { return (getFlags() & INST_READ) != 0; }
+
+ bool isLocked() { return (getFlags() & LOCKED) != 0; }
+
+ bool isSwap() { return (getFlags() & MEM_SWAP ||
+ getFlags() & MEM_SWAP_COND); }
+
+ bool isCondSwap() { return (getFlags() & MEM_SWAP_COND) != 0; }
+
+ bool inline isMisaligned() {return (!(getFlags() & NO_ALIGN_FAULT) &&
+ ((vaddr & 1) ||
+ (!(getFlags() & NO_HALF_WORD_ALIGN_FAULT)
+ && (vaddr & 0x2))));}
+
friend class Packet;
};
projects / gem5.git / blobdiff