Only issue responses if we aren;t already blocked

[gem5.git] / src / mem / request.hh

diff --git a/src/mem/request.hh b/src/mem/request.hh
index af1d6d8a852c2b7cbeb7c7b1b8adc439e855bfab..e54984fcde1f6d372399a68821eef07efbf5b472 100644 (file)
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -31,19 +31,24 @@
  */
 
 /**
- * @file Decleration of a request, the overall memory request consisting of
+ * @file
+ * Declaration of a request, the overall memory request consisting of
  the parts of the request that are persistent throughout the transaction.
  */
 
 #ifndef __MEM_REQUEST_HH__
 #define __MEM_REQUEST_HH__
 
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
+#include "sim/root.hh"
+
+#include <cassert>
 
 class Request;
 
 typedef Request* RequestPtr;
 
+
 /** The request is a Load locked/store conditional. */
 const unsigned LOCKED          = 0x001;
 /** The virtual address is also the physical address. */
@@ -62,6 +67,8 @@ const unsigned PF_EXCLUSIVE   = 0x100;
 const unsigned EVICT_NEXT      = 0x200;
 /** The request should ignore unaligned access faults */
 const unsigned NO_ALIGN_FAULT   = 0x400;
+/** The request was an instruction read. */
+const unsigned INST_READ        = 0x800;
 
 class Request
 {
@@ -224,6 +231,13 @@ class Request
     /** Accessor function for pc.*/
     Addr getPC() { assert(validPC); return pc; }
 
+    /** Accessor Function to Check Cacheability. */
+    bool isUncacheable() { return (getFlags() & UNCACHEABLE) != 0; }
+
+    bool isInstRead() { return (getFlags() & INST_READ) != 0; }
+
+    bool isLocked() { return (getFlags() & LOCKED) != 0; }
+
     friend class Packet;
 };