misc: Rename misc.(hh|cc) to logging.(hh|cc)

[gem5.git] / src / mem / ruby / slicc_interface / AbstractCacheEntry.hh

diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 18dc16ca8ab25447045c10a276f3a844be155201..f0e9500309dcfb3b94a7f64e960f01705ad61384 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -1,4 +1,3 @@
-
 /*
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
@@ -28,54 +27,71 @@
  */
 
 /*
- * $Id$
- *
- * Description: Common base class for a machine node.
- *
+ * Common base class for a machine node.
  */
 
-#ifndef AbstractCacheEntry_H
-#define AbstractCacheEntry_H
-
-#include "mem/ruby/common/Global.hh"
-#include "mem/ruby/common/Address.hh"
-#include "mem/protocol/AccessPermission.hh"
-
-class AbstractCacheEntry {
-public:
-  // Constructors
-  AbstractCacheEntry();
-
-  // Destructor, prevent it from instantiation
-  virtual ~AbstractCacheEntry() = 0;
+#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
+#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
 
-  // Public Methods
-
-  // The methods below are those called by ruby runtime, add when it is
-  // absolutely necessary and should all be virtual function.
+#include <iostream>
 
+#include "base/logging.hh"
+#include "mem/protocol/AccessPermission.hh"
+#include "mem/ruby/common/Address.hh"
+#include "mem/ruby/slicc_interface/AbstractEntry.hh"
 
-  virtual void print(ostream& out) const = 0;
+class DataBlock;
 
-  // Data Members (m_ prefix)
-  Address m_Address; // Address of this block, required by CacheMemory
-  Time m_LastRef; // Last time this block was referenced, required by CacheMemory
-  AccessPermission m_Permission; // Access permission for this block, required by CacheMemory
+class AbstractCacheEntry : public AbstractEntry
+{
+  public:
+    AbstractCacheEntry();
+    virtual ~AbstractCacheEntry() = 0;
+
+    // Get/Set permission of the entry
+    void changePermission(AccessPermission new_perm);
+
+    // The methods below are those called by ruby runtime, add when it
+    // is absolutely necessary and should all be virtual function.
+    virtual DataBlock& getDataBlk()
+    { panic("getDataBlk() not implemented!"); }
+
+    int validBlocks;
+    virtual int& getNumValidBlocks()
+    {
+        return validBlocks;
+    }
+
+    // Functions for locking and unlocking the cache entry.  These are required
+    // for supporting atomic memory accesses.
+    void setLocked(int context);
+    void clearLocked();
+    bool isLocked(int context) const;
+
+    void setSetIndex(uint32_t s) { m_set_index = s; }
+    uint32_t getSetIndex() const { return m_set_index; }
+
+    void setWayIndex(uint32_t s) { m_way_index = s; }
+    uint32_t getWayIndex() const { return m_way_index; }
+
+    // Address of this block, required by CacheMemory
+    Addr m_Address;
+    // Holds info whether the address is locked.
+    // Required for implementing LL/SC operations.
+    int m_locked;
+
+  private:
+    // Set and way coordinates of the entry within the cache memory object.
+    uint32_t m_set_index;
+    uint32_t m_way_index;
 };
 
-// Output operator declaration
-ostream& operator<<(ostream& out, const AbstractCacheEntry& obj);
-
-// ******************* Definitions *******************
-
-// Output operator definition
-extern inline
-ostream& operator<<(ostream& out, const AbstractCacheEntry& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const AbstractCacheEntry& obj)
 {
-  obj.print(out);
-  out << flush;
-  return out;
+    obj.print(out);
+    out << std::flush;
+    return out;
 }
 
-#endif //AbstractCacheEntry_H
-
+#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__