misc: Rename misc.(hh|cc) to logging.(hh|cc)

[gem5.git] / src / mem / ruby / slicc_interface / AbstractCacheEntry.hh

diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 2b318957ff2730dd39fe0077e4a8efd22f96986f..f0e9500309dcfb3b94a7f64e960f01705ad61384 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -35,7 +35,7 @@
 
 #include <iostream>
 
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
@@ -56,15 +56,34 @@ class AbstractCacheEntry : public AbstractEntry
     virtual DataBlock& getDataBlk()
     { panic("getDataBlk() not implemented!"); }
 
+    int validBlocks;
+    virtual int& getNumValidBlocks()
+    {
+        return validBlocks;
+    }
+
     // Functions for locking and unlocking the cache entry.  These are required
     // for supporting atomic memory accesses.
     void setLocked(int context);
     void clearLocked();
     bool isLocked(int context) const;
 
-    Addr m_Address; // Address of this block, required by CacheMemory
-    int m_locked; // Holds info whether the address is locked,
-                  // required for implementing LL/SC
+    void setSetIndex(uint32_t s) { m_set_index = s; }
+    uint32_t getSetIndex() const { return m_set_index; }
+
+    void setWayIndex(uint32_t s) { m_way_index = s; }
+    uint32_t getWayIndex() const { return m_way_index; }
+
+    // Address of this block, required by CacheMemory
+    Addr m_Address;
+    // Holds info whether the address is locked.
+    // Required for implementing LL/SC operations.
+    int m_locked;
+
+  private:
+    // Set and way coordinates of the entry within the cache memory object.
+    uint32_t m_set_index;
+    uint32_t m_way_index;
 };
 
 inline std::ostream&