misc: Rename misc.(hh|cc) to logging.(hh|cc)

[gem5.git] / src / mem / ruby / slicc_interface / AbstractCacheEntry.hh

diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 66cce58a1f1eb526574a62b5889b85259232d572..f0e9500309dcfb3b94a7f64e960f01705ad61384 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -35,9 +35,9 @@
 
 #include <iostream>
 
+#include "base/logging.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
 
 class DataBlock;
@@ -48,11 +48,42 @@ class AbstractCacheEntry : public AbstractEntry
     AbstractCacheEntry();
     virtual ~AbstractCacheEntry() = 0;
 
-    Address m_Address; // Address of this block, required by CacheMemory
-    Time m_LastRef; // Last time this block was referenced, required
-                    // by CacheMemory
-    AccessPermission m_Permission; // Access permission for this
-                                   // block, required by CacheMemory
+    // Get/Set permission of the entry
+    void changePermission(AccessPermission new_perm);
+
+    // The methods below are those called by ruby runtime, add when it
+    // is absolutely necessary and should all be virtual function.
+    virtual DataBlock& getDataBlk()
+    { panic("getDataBlk() not implemented!"); }
+
+    int validBlocks;
+    virtual int& getNumValidBlocks()
+    {
+        return validBlocks;
+    }
+
+    // Functions for locking and unlocking the cache entry.  These are required
+    // for supporting atomic memory accesses.
+    void setLocked(int context);
+    void clearLocked();
+    bool isLocked(int context) const;
+
+    void setSetIndex(uint32_t s) { m_set_index = s; }
+    uint32_t getSetIndex() const { return m_set_index; }
+
+    void setWayIndex(uint32_t s) { m_way_index = s; }
+    uint32_t getWayIndex() const { return m_way_index; }
+
+    // Address of this block, required by CacheMemory
+    Addr m_Address;
+    // Holds info whether the address is locked.
+    // Required for implementing LL/SC operations.
+    int m_locked;
+
+  private:
+    // Set and way coordinates of the entry within the cache memory object.
+    uint32_t m_set_index;
+    uint32_t m_way_index;
 };
 
 inline std::ostream&
@@ -64,4 +95,3 @@ operator<<(std::ostream& out, const AbstractCacheEntry& obj)
 }
 
 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
-