ruby: split CPU and GPU latency stats

[gem5.git] / src / mem / ruby / slicc_interface / AbstractController.cc

diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 64d581359d6d240c71eafd9495c38a8d4353c200..669fb30fb68b5402525feceb8710795981d084f0 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -30,8 +30,9 @@
 
 #include "debug/RubyQueue.hh"
 #include "mem/protocol/MemoryMsg.hh"
+#include "mem/ruby/system/RubySystem.hh"
 #include "mem/ruby/system/Sequencer.hh"
-#include "mem/ruby/system/System.hh"
+#include "mem/ruby/system/GPUCoalescer.hh"
 #include "sim/system.hh"
 
 AbstractController::AbstractController(const Params *p)
@@ -60,9 +61,6 @@ AbstractController::init()
         m_delayVCHistogram.push_back(new Stats::Histogram());
         m_delayVCHistogram[i]->init(10);
     }
-    if (getMemoryQueue()) {
-        getMemoryQueue()->setSender(this);
-    }
 }
 
 void
@@ -93,21 +91,21 @@ AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
 }
 
 void
-AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
+AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
 {
     if (m_waiting_buffers.count(addr) == 0) {
         MsgVecType* msgVec = new MsgVecType;
         msgVec->resize(m_in_ports, NULL);
         m_waiting_buffers[addr] = msgVec;
     }
-    DPRINTF(RubyQueue, "stalling %s port %d addr %s\n", buf, m_cur_in_port,
+    DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
             addr);
     assert(m_in_ports > m_cur_in_port);
     (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
 }
 
 void
-AbstractController::wakeUpBuffers(Address addr)
+AbstractController::wakeUpBuffers(Addr addr)
 {
     if (m_waiting_buffers.count(addr) > 0) {
         //
@@ -118,7 +116,8 @@ AbstractController::wakeUpBuffers(Address addr)
              in_port_rank >= 0;
              in_port_rank--) {
             if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
-                (*(m_waiting_buffers[addr]))[in_port_rank]->reanalyzeMessages(addr);
+                (*(m_waiting_buffers[addr]))[in_port_rank]->
+                    reanalyzeMessages(addr, clockEdge());
             }
         }
         delete m_waiting_buffers[addr];
@@ -127,7 +126,7 @@ AbstractController::wakeUpBuffers(Address addr)
 }
 
 void
-AbstractController::wakeUpAllBuffers(Address addr)
+AbstractController::wakeUpAllBuffers(Addr addr)
 {
     if (m_waiting_buffers.count(addr) > 0) {
         //
@@ -138,7 +137,8 @@ AbstractController::wakeUpAllBuffers(Address addr)
              in_port_rank >= 0;
              in_port_rank--) {
             if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
-                (*(m_waiting_buffers[addr]))[in_port_rank]->reanalyzeMessages(addr);
+                (*(m_waiting_buffers[addr]))[in_port_rank]->
+                    reanalyzeMessages(addr, clockEdge());
             }
         }
         delete m_waiting_buffers[addr];
@@ -168,7 +168,7 @@ AbstractController::wakeUpAllBuffers()
                   //
                   if (*vec_iter != NULL &&
                       (wokeUpMsgBufs.count(*vec_iter) == 0)) {
-                      (*vec_iter)->reanalyzeAllMessages();
+                      (*vec_iter)->reanalyzeAllMessages(clockEdge());
                       wokeUpMsgBufs.insert(*vec_iter);
                   }
              }
@@ -186,14 +186,14 @@ AbstractController::wakeUpAllBuffers()
 }
 
 void
-AbstractController::blockOnQueue(Address addr, MessageBuffer* port)
+AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
 {
     m_is_blocking = true;
     m_block_map[addr] = port;
 }
 
 void
-AbstractController::unblock(Address addr)
+AbstractController::unblock(Addr addr)
 {
     m_block_map.erase(addr);
     if (m_block_map.size() == 0) {
@@ -201,6 +201,12 @@ AbstractController::unblock(Address addr)
     }
 }
 
+bool
+AbstractController::isBlocked(Addr addr)
+{
+    return (m_block_map.count(addr) > 0);
+}
+
 BaseMasterPort &
 AbstractController::getMasterPort(const std::string &if_name,
                                   PortID idx)
@@ -209,11 +215,10 @@ AbstractController::getMasterPort(const std::string &if_name,
 }
 
 void
-AbstractController::queueMemoryRead(const MachineID &id, Address addr,
+AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
                                     Cycles latency)
 {
-    RequestPtr req = new Request(addr.getAddress(),
-                                 RubySystem::getBlockSizeBytes(), 0,
+    RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
                                  m_masterId);
 
     PacketPtr pkt = Packet::createRead(req);
@@ -234,11 +239,10 @@ AbstractController::queueMemoryRead(const MachineID &id, Address addr,
 }
 
 void
-AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
+AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
                                      Cycles latency, const DataBlock &block)
 {
-    RequestPtr req = new Request(addr.getAddress(),
-                                 RubySystem::getBlockSizeBytes(), 0,
+    RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
                                  m_masterId);
 
     PacketPtr pkt = Packet::createWrite(req);
@@ -262,18 +266,17 @@ AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
 }
 
 void
-AbstractController::queueMemoryWritePartial(const MachineID &id, Address addr,
+AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
                                             Cycles latency,
                                             const DataBlock &block, int size)
 {
-    RequestPtr req = new Request(addr.getAddress(),
-                                 RubySystem::getBlockSizeBytes(), 0,
+    RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
                                  m_masterId);
 
     PacketPtr pkt = Packet::createWrite(req);
     uint8_t *newData = new uint8_t[size];
     pkt->dataDynamic(newData);
-    memcpy(newData, block.getData(addr.getOffset(), size), size);
+    memcpy(newData, block.getData(getOffset(addr), size), size);
 
     SenderState *s = new SenderState(id);
     pkt->pushSenderState(s);
@@ -310,7 +313,7 @@ AbstractController::recvTimingResp(PacketPtr pkt)
     assert(pkt->isResponse());
 
     std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
-    (*msg).m_addr.setAddress(pkt->getAddr());
+    (*msg).m_addr = pkt->getAddr();
     (*msg).m_Sender = m_machineID;
 
     SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
@@ -331,7 +334,8 @@ AbstractController::recvTimingResp(PacketPtr pkt)
         panic("Incorrect packet type received from memory controller!");
     }
 
-    getMemoryQueue()->enqueue(msg);
+    getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
+    delete pkt->req;
     delete pkt;
 }