arch, cpu, dev, gpu, mem, sim, python: start using getPort.

[gem5.git] / src / mem / ruby / slicc_interface / AbstractController.hh

diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 35cd3d2a55b75134a7f304f1f29b9f52e67fba65..5e39a28d2344827794fb80394420c7f5332ef8ee 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -126,8 +126,8 @@ class AbstractController : public MemObject, public Consumer
     virtual void initNetQueues() = 0;
 
     /** A function used to return the port associated with this bus object. */
-    BaseMasterPort& getMasterPort(const std::string& if_name,
-                                  PortID idx = InvalidPortID);
+    Port &getPort(const std::string &if_name,
+                  PortID idx=InvalidPortID);
 
     void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
     void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,