* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/*
- * CacheMemory.h
- *
- * Description:
- *
- * $Id: CacheMemory.h,v 3.7 2004/06/18 20:15:15 beckmann Exp $
- *
- */
+#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
+#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
-#ifndef CACHEMEMORY_H
-#define CACHEMEMORY_H
+#include <iostream>
+#include <string>
+#include <vector>
-#include "mem/ruby/slicc_interface/AbstractChip.hh"
-#include "mem/ruby/common/Global.hh"
+#include "base/hashmap.hh"
#include "mem/protocol/AccessPermission.hh"
+#include "mem/protocol/GenericRequestType.hh"
+#include "mem/protocol/MachineType.hh"
+#include "mem/protocol/RubyRequest.hh"
+#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
-#include "mem/ruby/recorder/CacheRecorder.hh"
-#include "mem/protocol/CacheRequestType.hh"
-#include "mem/gems_common/Vector.hh"
#include "mem/ruby/common/DataBlock.hh"
-#include "mem/protocol/MachineType.hh"
+#include "mem/ruby/common/Global.hh"
+#include "mem/ruby/profiler/CacheProfiler.hh"
+#include "mem/ruby/recorder/CacheRecorder.hh"
+#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
+#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
-#include "mem/ruby/system/PseudoLRUPolicy.hh"
#include "mem/ruby/system/LRUPolicy.hh"
-#include <vector>
-
-template<class ENTRY>
-class CacheMemory {
-public:
-
- // Constructors
- CacheMemory(AbstractChip* chip_ptr, int numSetBits, int cacheAssoc, const MachineType machType, const string& description);
-
- // Destructor
- ~CacheMemory();
-
- // Public Methods
- void printConfig(ostream& out);
-
- // perform a cache access and see if we hit or not. Return true on a hit.
- bool tryCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
-
- // similar to above, but doesn't require full access check
- bool testCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
-
- // tests to see if an address is present in the cache
- bool isTagPresent(const Address& address) const;
-
- // Returns true if there is:
- // a) a tag match on this address or there is
- // b) an unused line in the same cache "way"
- bool cacheAvail(const Address& address) const;
-
- // find an unused entry and sets the tag appropriate for the address
- void allocate(const Address& address);
-
- // Explicitly free up this address
- void deallocate(const Address& address);
-
- // Returns with the physical address of the conflicting cache line
- Address cacheProbe(const Address& address) const;
-
- // looks an address up in the cache
- ENTRY& lookup(const Address& address);
- const ENTRY& lookup(const Address& address) const;
-
- // Get/Set permission of cache block
- AccessPermission getPermission(const Address& address) const;
- void changePermission(const Address& address, AccessPermission new_perm);
-
- // Hook for checkpointing the contents of the cache
- void recordCacheContents(CacheRecorder& tr) const;
- void setAsInstructionCache(bool is_icache) { m_is_instruction_cache = is_icache; }
-
- // Set this address to most recently used
- void setMRU(const Address& address);
+#include "mem/ruby/system/PseudoLRUPolicy.hh"
+#include "mem/ruby/system/System.hh"
+#include "params/RubyCache.hh"
+#include "sim/sim_object.hh"
- void getMemoryValue(const Address& addr, char* value,
- unsigned int size_in_bytes );
- void setMemoryValue(const Address& addr, char* value,
- unsigned int size_in_bytes );
+class CacheMemory : public SimObject
+{
+ public:
+ typedef RubyCacheParams Params;
+ CacheMemory(const Params *p);
+ ~CacheMemory();
- // Print cache contents
- void print(ostream& out) const;
- void printData(ostream& out) const;
+ void init();
-private:
- // Private Methods
+ // Public Methods
+ void printConfig(std::ostream& out);
- // convert a Address to its location in the cache
- Index addressToCacheSet(const Address& address) const;
+ // perform a cache access and see if we hit or not. Return true on a hit.
+ bool tryCacheAccess(const Address& address, RubyRequestType type,
+ DataBlock*& data_ptr);
- // Given a cache tag: returns the index of the tag in a set.
- // returns -1 if the tag is not found.
- int findTagInSet(Index line, const Address& tag) const;
- int findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const;
+ // similar to above, but doesn't require full access check
+ bool testCacheAccess(const Address& address, RubyRequestType type,
+ DataBlock*& data_ptr);
- // Private copy constructor and assignment operator
- CacheMemory(const CacheMemory& obj);
- CacheMemory& operator=(const CacheMemory& obj);
+ // tests to see if an address is present in the cache
+ bool isTagPresent(const Address& address) const;
- // Data Members (m_prefix)
- AbstractChip* m_chip_ptr;
- MachineType m_machType;
- string m_description;
- bool m_is_instruction_cache;
+ // Returns true if there is:
+ // a) a tag match on this address or there is
+ // b) an unused line in the same cache "way"
+ bool cacheAvail(const Address& address) const;
- // The first index is the # of cache lines.
- // The second index is the the amount associativity.
- Vector<Vector<ENTRY> > m_cache;
+ // find an unused entry and sets the tag appropriate for the address
+ AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
+ void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
+ {
+ allocate(address, new_entry);
+ }
- AbstractReplacementPolicy *m_replacementPolicy_ptr;
+ // Explicitly free up this address
+ void deallocate(const Address& address);
- int m_cache_num_sets;
- int m_cache_num_set_bits;
- int m_cache_assoc;
-};
+ // Returns with the physical address of the conflicting cache line
+ Address cacheProbe(const Address& address) const;
-// Output operator declaration
-//ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj);
+ // looks an address up in the cache
+ AbstractCacheEntry* lookup(const Address& address);
+ const AbstractCacheEntry* lookup(const Address& address) const;
-// ******************* Definitions *******************
+ int getLatency() const { return m_latency; }
-// Output operator definition
-template<class ENTRY>
-inline
-ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj)
-{
- obj.print(out);
- out << flush;
- return out;
-}
+ // Hook for checkpointing the contents of the cache
+ void recordCacheContents(CacheRecorder& tr) const;
+ void
+ setAsInstructionCache(bool is_icache)
+ {
+ m_is_instruction_only_cache = is_icache;
+ }
+ // Set this address to most recently used
+ void setMRU(const Address& address);
-// ****************************************************************
+ void profileMiss(const RubyRequest & msg);
-template<class ENTRY>
-inline
-CacheMemory<ENTRY>::CacheMemory(AbstractChip* chip_ptr, int numSetBits,
- int cacheAssoc, const MachineType machType, const string& description)
+ void profileGenericRequest(GenericRequestType requestType,
+ RubyAccessMode accessType,
+ PrefetchBit pfBit);
-{
- //cout << "CacheMemory constructor numThreads = " << numThreads << endl;
- m_chip_ptr = chip_ptr;
- m_machType = machType;
- m_description = MachineType_to_string(m_machType)+"_"+description;
- m_cache_num_set_bits = numSetBits;
- m_cache_num_sets = 1 << numSetBits;
- m_cache_assoc = cacheAssoc;
- m_is_instruction_cache = false;
-
- m_cache.setSize(m_cache_num_sets);
- if(strcmp(g_REPLACEMENT_POLICY, "PSEDUO_LRU") == 0)
- m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc);
- else if(strcmp(g_REPLACEMENT_POLICY, "LRU") == 0)
- m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc);
- else
- assert(false);
- for (int i = 0; i < m_cache_num_sets; i++) {
- m_cache[i].setSize(m_cache_assoc);
- for (int j = 0; j < m_cache_assoc; j++) {
- m_cache[i][j].m_Address.setAddress(0);
- m_cache[i][j].m_Permission = AccessPermission_NotPresent;
- }
- }
-
-
- // cout << "Before setting trans address list size" << endl;
- //create a trans address for each SMT thread
-// m_trans_address_list.setSize(numThreads);
-// for(int i=0; i < numThreads; ++i){
-// cout << "Setting list size for list " << i << endl;
-// m_trans_address_list[i].setSize(30);
-// }
- //cout << "CacheMemory constructor finished" << endl;
-}
-
-template<class ENTRY>
-inline
-CacheMemory<ENTRY>::~CacheMemory()
-{
- if(m_replacementPolicy_ptr != NULL)
- delete m_replacementPolicy_ptr;
-}
+ void getMemoryValue(const Address& addr, char* value,
+ unsigned int size_in_bytes);
+ void setMemoryValue(const Address& addr, char* value,
+ unsigned int size_in_bytes);
-template<class ENTRY>
-inline
-void CacheMemory<ENTRY>::printConfig(ostream& out)
-{
- out << "Cache config: " << m_description << endl;
- out << " cache_associativity: " << m_cache_assoc << endl;
- out << " num_cache_sets_bits: " << m_cache_num_set_bits << endl;
- const int cache_num_sets = 1 << m_cache_num_set_bits;
- out << " num_cache_sets: " << cache_num_sets << endl;
- out << " cache_set_size_bytes: " << cache_num_sets * RubyConfig::dataBlockBytes() << endl;
- out << " cache_set_size_Kbytes: "
- << double(cache_num_sets * RubyConfig::dataBlockBytes()) / (1<<10) << endl;
- out << " cache_set_size_Mbytes: "
- << double(cache_num_sets * RubyConfig::dataBlockBytes()) / (1<<20) << endl;
- out << " cache_size_bytes: "
- << cache_num_sets * RubyConfig::dataBlockBytes() * m_cache_assoc << endl;
- out << " cache_size_Kbytes: "
- << double(cache_num_sets * RubyConfig::dataBlockBytes() * m_cache_assoc) / (1<<10) << endl;
- out << " cache_size_Mbytes: "
- << double(cache_num_sets * RubyConfig::dataBlockBytes() * m_cache_assoc) / (1<<20) << endl;
-}
-
-// PRIVATE METHODS
-
-// convert a Address to its location in the cache
-template<class ENTRY>
-inline
-Index CacheMemory<ENTRY>::addressToCacheSet(const Address& address) const
-{
- assert(address == line_address(address));
- Index temp = -1;
- switch (m_machType) {
- case MACHINETYPE_L1CACHE_ENUM:
- temp = map_address_to_L1CacheSet(address, m_cache_num_set_bits);
- break;
- case MACHINETYPE_L2CACHE_ENUM:
- temp = map_address_to_L2CacheSet(address, m_cache_num_set_bits);
- break;
- default:
- ERROR_MSG("Don't recognize m_machType");
- }
- assert(temp < m_cache_num_sets);
- assert(temp >= 0);
- return temp;
-}
-
-// Given a cache index: returns the index of the tag in a set.
-// returns -1 if the tag is not found.
-template<class ENTRY>
-inline
-int CacheMemory<ENTRY>::findTagInSet(Index cacheSet, const Address& tag) const
-{
- assert(tag == line_address(tag));
- // search the set for the tags
- for (int i=0; i < m_cache_assoc; i++) {
- if ((m_cache[cacheSet][i].m_Address == tag) &&
- (m_cache[cacheSet][i].m_Permission != AccessPermission_NotPresent)) {
- return i;
- }
- }
- return -1; // Not found
-}
-
-// Given a cache index: returns the index of the tag in a set.
-// returns -1 if the tag is not found.
-template<class ENTRY>
-inline
-int CacheMemory<ENTRY>::findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const
-{
- assert(tag == line_address(tag));
- // search the set for the tags
- for (int i=0; i < m_cache_assoc; i++) {
- if (m_cache[cacheSet][i].m_Address == tag)
- return i;
- }
- return -1; // Not found
-}
-
-// PUBLIC METHODS
-template<class ENTRY>
-inline
-bool CacheMemory<ENTRY>::tryCacheAccess(const Address& address,
- CacheRequestType type,
- DataBlock*& data_ptr)
-{
- assert(address == line_address(address));
- DEBUG_EXPR(CACHE_COMP, HighPrio, address);
- Index cacheSet = addressToCacheSet(address);
- int loc = findTagInSet(cacheSet, address);
- if(loc != -1){ // Do we even have a tag match?
- ENTRY& entry = m_cache[cacheSet][loc];
- m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
- data_ptr = &(entry.getDataBlk());
-
- if(entry.m_Permission == AccessPermission_Read_Write) {
- return true;
- }
- if ((entry.m_Permission == AccessPermission_Read_Only) &&
- (type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) {
- return true;
- }
- // The line must not be accessible
- }
- data_ptr = NULL;
- return false;
-}
-
-template<class ENTRY>
-inline
-bool CacheMemory<ENTRY>::testCacheAccess(const Address& address,
- CacheRequestType type,
- DataBlock*& data_ptr)
-{
- assert(address == line_address(address));
- DEBUG_EXPR(CACHE_COMP, HighPrio, address);
- Index cacheSet = addressToCacheSet(address);
- int loc = findTagInSet(cacheSet, address);
- if(loc != -1){ // Do we even have a tag match?
- ENTRY& entry = m_cache[cacheSet][loc];
- m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
- data_ptr = &(entry.getDataBlk());
-
- return (m_cache[cacheSet][loc].m_Permission != AccessPermission_NotPresent);
- }
- data_ptr = NULL;
- return false;
-}
-
-// tests to see if an address is present in the cache
-template<class ENTRY>
-inline
-bool CacheMemory<ENTRY>::isTagPresent(const Address& address) const
-{
- assert(address == line_address(address));
- Index cacheSet = addressToCacheSet(address);
- int location = findTagInSet(cacheSet, address);
-
- if (location == -1) {
- // We didn't find the tag
- DEBUG_EXPR(CACHE_COMP, LowPrio, address);
- DEBUG_MSG(CACHE_COMP, LowPrio, "No tag match");
- return false;
- }
- DEBUG_EXPR(CACHE_COMP, LowPrio, address);
- DEBUG_MSG(CACHE_COMP, LowPrio, "found");
- return true;
-}
-
-// Returns true if there is:
-// a) a tag match on this address or there is
-// b) an unused line in the same cache "way"
-template<class ENTRY>
-inline
-bool CacheMemory<ENTRY>::cacheAvail(const Address& address) const
-{
- assert(address == line_address(address));
+ void setLocked (const Address& addr, int context);
+ void clearLocked (const Address& addr);
+ bool isLocked (const Address& addr, int context);
+ // Print cache contents
+ void print(std::ostream& out) const;
+ void printData(std::ostream& out) const;
- Index cacheSet = addressToCacheSet(address);
+ void clearStats() const;
+ void printStats(std::ostream& out) const;
- for (int i=0; i < m_cache_assoc; i++) {
- if (m_cache[cacheSet][i].m_Address == address) {
- // Already in the cache
- return true;
- }
+ private:
+ // convert a Address to its location in the cache
+ Index addressToCacheSet(const Address& address) const;
- if (m_cache[cacheSet][i].m_Permission == AccessPermission_NotPresent) {
- // We found an empty entry
- return true;
- }
- }
- return false;
-}
+ // Given a cache tag: returns the index of the tag in a set.
+ // returns -1 if the tag is not found.
+ int findTagInSet(Index line, const Address& tag) const;
+ int findTagInSetIgnorePermissions(Index cacheSet,
+ const Address& tag) const;
-template<class ENTRY>
-inline
-void CacheMemory<ENTRY>::allocate(const Address& address)
-{
- assert(address == line_address(address));
- assert(!isTagPresent(address));
- assert(cacheAvail(address));
- DEBUG_EXPR(CACHE_COMP, HighPrio, address);
-
- // Find the first open slot
- Index cacheSet = addressToCacheSet(address);
- for (int i=0; i < m_cache_assoc; i++) {
- if (m_cache[cacheSet][i].m_Permission == AccessPermission_NotPresent) {
- m_cache[cacheSet][i] = ENTRY(); // Init entry
- m_cache[cacheSet][i].m_Address = address;
- m_cache[cacheSet][i].m_Permission = AccessPermission_Invalid;
-
- m_replacementPolicy_ptr->touch(cacheSet, i, g_eventQueue_ptr->getTime());
-
- return;
- }
- }
- ERROR_MSG("Allocate didn't find an available entry");
-}
-
-template<class ENTRY>
-inline
-void CacheMemory<ENTRY>::deallocate(const Address& address)
-{
- assert(address == line_address(address));
- assert(isTagPresent(address));
- DEBUG_EXPR(CACHE_COMP, HighPrio, address);
- lookup(address).m_Permission = AccessPermission_NotPresent;
-}
-
-// Returns with the physical address of the conflicting cache line
-template<class ENTRY>
-inline
-Address CacheMemory<ENTRY>::cacheProbe(const Address& address) const
-{
- assert(address == line_address(address));
- assert(!cacheAvail(address));
+ // Private copy constructor and assignment operator
+ CacheMemory(const CacheMemory& obj);
+ CacheMemory& operator=(const CacheMemory& obj);
- Index cacheSet = addressToCacheSet(address);
- return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)].m_Address;
-}
+ private:
+ const std::string m_cache_name;
+ int m_latency;
-// looks an address up in the cache
-template<class ENTRY>
-inline
-ENTRY& CacheMemory<ENTRY>::lookup(const Address& address)
-{
- assert(address == line_address(address));
- Index cacheSet = addressToCacheSet(address);
- int loc = findTagInSet(cacheSet, address);
- assert(loc != -1);
- return m_cache[cacheSet][loc];
-}
-
-// looks an address up in the cache
-template<class ENTRY>
-inline
-const ENTRY& CacheMemory<ENTRY>::lookup(const Address& address) const
-{
- assert(address == line_address(address));
- Index cacheSet = addressToCacheSet(address);
- int loc = findTagInSet(cacheSet, address);
- assert(loc != -1);
- return m_cache[cacheSet][loc];
-}
-
-template<class ENTRY>
-inline
-AccessPermission CacheMemory<ENTRY>::getPermission(const Address& address) const
-{
- assert(address == line_address(address));
- return lookup(address).m_Permission;
-}
+ // Data Members (m_prefix)
+ bool m_is_instruction_only_cache;
+ bool m_is_data_only_cache;
-template<class ENTRY>
-inline
-void CacheMemory<ENTRY>::changePermission(const Address& address, AccessPermission new_perm)
-{
- assert(address == line_address(address));
- lookup(address).m_Permission = new_perm;
- assert(getPermission(address) == new_perm);
-}
-
-// Sets the most recently used bit for a cache block
-template<class ENTRY>
-inline
-void CacheMemory<ENTRY>::setMRU(const Address& address)
-{
- Index cacheSet;
+ // The first index is the # of cache lines.
+ // The second index is the the amount associativity.
+ m5::hash_map<Address, int> m_tag_index;
+ std::vector<std::vector<AbstractCacheEntry*> > m_cache;
- cacheSet = addressToCacheSet(address);
- m_replacementPolicy_ptr->touch(cacheSet,
- findTagInSet(cacheSet, address),
- g_eventQueue_ptr->getTime());
-}
+ AbstractReplacementPolicy *m_replacementPolicy_ptr;
-template<class ENTRY>
-inline
-void CacheMemory<ENTRY>::recordCacheContents(CacheRecorder& tr) const
-{
- for (int i = 0; i < m_cache_num_sets; i++) {
- for (int j = 0; j < m_cache_assoc; j++) {
- AccessPermission perm = m_cache[i][j].m_Permission;
- CacheRequestType request_type = CacheRequestType_NULL;
- if (perm == AccessPermission_Read_Only) {
- if (m_is_instruction_cache) {
- request_type = CacheRequestType_IFETCH;
- } else {
- request_type = CacheRequestType_LD;
- }
- } else if (perm == AccessPermission_Read_Write) {
- request_type = CacheRequestType_ST;
- }
-
- if (request_type != CacheRequestType_NULL) {
- tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address,
- Address(0), request_type, m_replacementPolicy_ptr->getLastAccess(i, j));
- }
- }
- }
-}
+ CacheProfiler* m_profiler_ptr;
-template<class ENTRY>
-inline
-void CacheMemory<ENTRY>::print(ostream& out) const
-{
- out << "Cache dump: " << m_description << endl;
- for (int i = 0; i < m_cache_num_sets; i++) {
- for (int j = 0; j < m_cache_assoc; j++) {
- out << " Index: " << i
- << " way: " << j
- << " entry: " << m_cache[i][j] << endl;
- }
- }
-}
+ int m_cache_size;
+ std::string m_policy;
+ int m_cache_num_sets;
+ int m_cache_num_set_bits;
+ int m_cache_assoc;
+ int m_start_index_bit;
+};
-template<class ENTRY>
-inline
-void CacheMemory<ENTRY>::printData(ostream& out) const
-{
- out << "printData() not supported" << endl;
-}
-
-template<class ENTRY>
-void CacheMemory<ENTRY>::getMemoryValue(const Address& addr, char* value,
- unsigned int size_in_bytes ){
- ENTRY entry = lookup(line_address(addr));
- unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
- for(unsigned int i=0; i<size_in_bytes; ++i){
- value[i] = entry.m_DataBlk.getByte(i + startByte);
- }
-}
-
-template<class ENTRY>
-void CacheMemory<ENTRY>::setMemoryValue(const Address& addr, char* value,
- unsigned int size_in_bytes ){
- ENTRY& entry = lookup(line_address(addr));
- unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
- assert(size_in_bytes > 0);
- for(unsigned int i=0; i<size_in_bytes; ++i){
- entry.m_DataBlk.setByte(i + startByte, value[i]);
- }
-
- entry = lookup(line_address(addr));
-}
-
-#endif //CACHEMEMORY_H
+#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
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