sim-ruby: checkpointing fixes and dependent eventq improvements

[gem5.git] / src / mem / ruby / system / PerfectCacheMemory.hh

diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh
index b04a6471701e984dc6ae6073c41d812c31218501..b880b643486e39ab6de37953ff2a9d4f07d6ebcf 100644 (file)
--- a/src/mem/ruby/system/PerfectCacheMemory.hh
+++ b/src/mem/ruby/system/PerfectCacheMemory.hh
@@ -32,7 +32,6 @@
 #include "base/hashmap.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
 
 template<class ENTRY>
 struct PerfectCacheLineState
@@ -57,10 +56,6 @@ class PerfectCacheMemory
 
     static void printConfig(std::ostream& out);
 
-    // perform a cache access and see if we hit or not.  Return true
-    // on a hit.
-    bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
-
     // tests to see if an address is present in the cache
     bool isTagPresent(const Address& address) const;
 
@@ -118,15 +113,6 @@ PerfectCacheMemory<ENTRY>::printConfig(std::ostream& out)
 {
 }
 
-template<class ENTRY>
-inline bool
-PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg,
-                                          bool& block_stc, ENTRY*& entry)
-{
-    panic("not implemented");
-    return true;
-}
-
 // tests to see if an address is present in the cache
 template<class ENTRY>
 inline bool
@@ -149,7 +135,7 @@ inline void
 PerfectCacheMemory<ENTRY>::allocate(const Address& address)
 {
     PerfectCacheLineState<ENTRY> line_state;
-    line_state.m_permission = AccessPermission_Busy;
+    line_state.m_permission = AccessPermission_Invalid;
     line_state.m_entry = ENTRY();
     m_map[line_address(address)] = line_state;
 }