sim-ruby: checkpointing fixes and dependent eventq improvements
[gem5.git] / src / mem / ruby / system / Sequencer.hh
index 2b1f023c591dc0676deb6c9152d5d9f94540f36d..29625899483ca3c9ba5b53e2594cc3fb30dfe4e9 100644 (file)
@@ -1,4 +1,3 @@
-
 /*
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/*
- * $Id: Sequencer.hh 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $
- *
- * Description:
- *
- */
+#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
+#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
 
-#ifndef SEQUENCER_H
-#define SEQUENCER_H
+#include <iostream>
 
-#include "mem/ruby/common/Global.hh"
-#include "mem/ruby/common/Consumer.hh"
-#include "mem/protocol/CacheRequestType.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "base/hashmap.hh"
 #include "mem/protocol/GenericMachineType.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/ruby/system/RubyPort.hh"
-#include "mem/gems_common/Map.hh"
+#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/system/RubyPort.hh"
 
 class DataBlock;
-class CacheMsg;
-class MachineID;
 class CacheMemory;
-class AbstractController;
-
-struct SequencerRequest {
-  RubyRequest ruby_request;
-  int64_t id;
-  Time issue_time;
-
-  SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
-    : ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
-  {}
-};
-
-class Sequencer : public Consumer, public RubyPort {
-public:
-  // Constructors
-  Sequencer(const string & name);
-  void init(const vector<string> & argv);
-
-  // Destructor
-  ~Sequencer();
-
-  // Public Methods
-  void wakeup(); // Used only for deadlock detection
 
-  void printConfig(ostream& out) const;
+struct RubySequencerParams;
 
-  void printProgress(ostream& out) const;
-
-  void writeCallback(const Address& address, DataBlock& data);
-  void readCallback(const Address& address, DataBlock& data);
-
-  // called by Tester or Simics
-  int64_t makeRequest(const RubyRequest & request);
-  bool isReady(const RubyRequest& request);
-  bool empty() const;
-
-  void print(ostream& out) const;
-  void checkCoherence(const Address& address);
-
-  //  bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
-  //  bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
-
-  void removeRequest(SequencerRequest* request);
-private:
-  // Private Methods
-  bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
-  void issueRequest(const RubyRequest& request);
-
-  void hitCallback(SequencerRequest* request, DataBlock& data);
-  bool insertRequest(SequencerRequest* request);
-
-
-  // Private copy constructor and assignment operator
-  Sequencer(const Sequencer& obj);
-  Sequencer& operator=(const Sequencer& obj);
-
-private:
-  int m_max_outstanding_requests;
-  int m_deadlock_threshold;
-
-  AbstractController* m_controller;
-  MessageBuffer* m_mandatory_q_ptr;
-  CacheMemory* m_dataCache_ptr;
-  CacheMemory* m_instCache_ptr;
-
-  // indicates what processor on the chip this sequencer is associated with
-  int m_version;
-  int m_controller_type;
+struct SequencerRequest
+{
+    PacketPtr pkt;
+    RubyRequestType m_type;
+    Time issue_time;
 
-  Map<Address, SequencerRequest*> m_writeRequestTable;
-  Map<Address, SequencerRequest*> m_readRequestTable;
-  // Global outstanding request count, across all request tables
-  int m_outstanding_count;
-  bool m_deadlock_check_scheduled;
-  int m_servicing_atomic;
-  int m_atomics_counter;
+    SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, Time _issue_time)
+        : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
+    {}
 };
 
-// Output operator declaration
-ostream& operator<<(ostream& out, const Sequencer& obj);
+std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
 
-// ******************* Definitions *******************
+class Sequencer : public RubyPort, public Consumer
+{
+  public:
+    typedef RubySequencerParams Params;
+    Sequencer(const Params *);
+    ~Sequencer();
+
+    // Public Methods
+    void wakeup(); // Used only for deadlock detection
+
+    void printConfig(std::ostream& out) const;
+
+    void printProgress(std::ostream& out) const;
+
+    void writeCallback(const Address& address, DataBlock& data);
+
+    void writeCallback(const Address& address, 
+                       GenericMachineType mach, 
+                       DataBlock& data);
+
+    void writeCallback(const Address& address, 
+                       GenericMachineType mach, 
+                       DataBlock& data,
+                       Time initialRequestTime,
+                       Time forwardRequestTime,
+                       Time firstResponseTime);
+
+    void readCallback(const Address& address, DataBlock& data);
+
+    void readCallback(const Address& address, 
+                      GenericMachineType mach, 
+                      DataBlock& data);
+
+    void readCallback(const Address& address, 
+                      GenericMachineType mach, 
+                      DataBlock& data,
+                      Time initialRequestTime,
+                      Time forwardRequestTime,
+                      Time firstResponseTime);
+
+    RequestStatus makeRequest(PacketPtr pkt);
+    bool empty() const;
+    int outstandingCount() const { return m_outstanding_count; }
+    bool
+    isDeadlockEventScheduled() const
+    {
+        return deadlockCheckEvent.scheduled();
+    }
+
+    void
+    descheduleDeadlockEvent()
+    {
+        deschedule(deadlockCheckEvent);
+    }
+
+    void print(std::ostream& out) const;
+    void printStats(std::ostream& out) const;
+    void checkCoherence(const Address& address);
+
+    void markRemoved();
+    void removeRequest(SequencerRequest* request);
+    void evictionCallback(const Address& address);
+
+  private:
+    void issueRequest(PacketPtr pkt, RubyRequestType type);
+
+    void hitCallback(SequencerRequest* request, 
+                     GenericMachineType mach,
+                     DataBlock& data,
+                     bool success,
+                     Time initialRequestTime,
+                     Time forwardRequestTime,
+                     Time firstResponseTime);
+
+    RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
+
+    bool handleLlsc(const Address& address, SequencerRequest* request);
+
+    // Private copy constructor and assignment operator
+    Sequencer(const Sequencer& obj);
+    Sequencer& operator=(const Sequencer& obj);
+
+  private:
+    int m_max_outstanding_requests;
+    int m_deadlock_threshold;
+
+    CacheMemory* m_dataCache_ptr;
+    CacheMemory* m_instCache_ptr;
+
+    typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
+    RequestTable m_writeRequestTable;
+    RequestTable m_readRequestTable;
+    // Global outstanding request count, across all request tables
+    int m_outstanding_count;
+    bool m_deadlock_check_scheduled;
+
+    int m_store_waiting_on_load_cycles;
+    int m_store_waiting_on_store_cycles;
+    int m_load_waiting_on_store_cycles;
+    int m_load_waiting_on_load_cycles;
+
+    bool m_usingNetworkTester;
+
+    class SequencerWakeupEvent : public Event
+    {
+      private:
+        Sequencer *m_sequencer_ptr;
+
+      public:
+        SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {}
+        void process() { m_sequencer_ptr->wakeup(); }
+        const char *description() const { return "Sequencer deadlock check"; }
+    };
+
+    SequencerWakeupEvent deadlockCheckEvent;
+};
 
-// Output operator definition
-extern inline
-ostream& operator<<(ostream& out, const Sequencer& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const Sequencer& obj)
 {
-  obj.print(out);
-  out << flush;
-  return out;
+    obj.print(out);
+    out << std::flush;
+    return out;
 }
 
-#endif //SEQUENCER_H
-
+#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__