#include <cstdio>
#include "base/intmath.hh"
-#include "base/output.hh"
+#include "base/statistics.hh"
#include "debug/RubyCacheTrace.hh"
+#include "debug/RubySystem.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/profiler/Profiler.hh"
int RubySystem::m_random_seed;
bool RubySystem::m_randomization;
-Tick RubySystem::m_clock;
int RubySystem::m_block_size_bytes;
int RubySystem::m_block_size_bits;
uint64 RubySystem::m_memory_size_bytes;
int RubySystem::m_memory_size_bits;
-Network* RubySystem::m_network_ptr;
-Profiler* RubySystem::m_profiler_ptr;
-MemoryVector* RubySystem::m_mem_vec_ptr;
-
RubySystem::RubySystem(const Params *p)
- : SimObject(p)
+ : ClockedObject(p)
{
if (g_system_ptr != NULL)
fatal("Only one RubySystem object currently allowed.\n");
m_random_seed = p->random_seed;
srandom(m_random_seed);
m_randomization = p->randomization;
- m_clock = p->clock;
m_block_size_bytes = p->block_size_bytes;
assert(isPowerOf2(m_block_size_bytes));
m_memory_size_bits = floorLog2(m_memory_size_bytes);
}
- g_eventQueue_ptr = new RubyEventQueue(p->eventq, m_clock);
g_system_ptr = this;
if (p->no_mem_vec) {
m_mem_vec_ptr = NULL;
m_mem_vec_ptr->resize(m_memory_size_bytes);
}
- //
- // Print ruby configuration and stats at exit
- //
- RubyExitCallback* rubyExitCB = new RubyExitCallback(p->stats_filename);
- registerExitCallback(rubyExitCB);
+ // Print ruby configuration and stats at exit and when asked for
+ Stats::registerDumpCallback(new RubyDumpStatsCallback(p->stats_filename,
+ this));
+
m_warmup_enabled = false;
m_cooldown_enabled = false;
}
RubySystem::init()
{
m_profiler_ptr->clearStats();
+ m_network_ptr->clearStats();
}
void
void
RubySystem::registerMemController(MemoryControl *mc) {
- m_memory_controller = mc;
+ m_memory_controller_vec.push_back(mc);
}
RubySystem::~RubySystem()
delete m_mem_vec_ptr;
}
-void
-RubySystem::printSystemConfig(ostream & out)
-{
- out << "RubySystem config:" << endl
- << " random_seed: " << m_random_seed << endl
- << " randomization: " << m_randomization << endl
- << " cycle_period: " << m_clock << endl
- << " block_size_bytes: " << m_block_size_bytes << endl
- << " block_size_bits: " << m_block_size_bits << endl
- << " memory_size_bytes: " << m_memory_size_bytes << endl
- << " memory_size_bits: " << m_memory_size_bits << endl;
-}
-
-void
-RubySystem::printConfig(ostream& out)
-{
- out << "\n================ Begin RubySystem Configuration Print ================\n\n";
- printSystemConfig(out);
- m_network_ptr->printConfig(out);
- m_profiler_ptr->printConfig(out);
- out << "\n================ End RubySystem Configuration Print ================\n\n";
-}
-
void
RubySystem::printStats(ostream& out)
{
}
void
-RubySystem::writeCompressedTrace(uint8* raw_data, string filename,
+RubySystem::writeCompressedTrace(uint8_t *raw_data, string filename,
uint64 uncompressed_trace_size)
{
// Create the checkpoint file for the memory
// Restore curTick
curTick(curtick_original);
- uint8* raw_data = NULL;
+ uint8_t *raw_data = NULL;
if (m_mem_vec_ptr != NULL) {
uint64 memory_trace_size = m_mem_vec_ptr->collatePages(raw_data);
}
void
-RubySystem::readCompressedTrace(string filename, uint8*& raw_data,
+RubySystem::readCompressedTrace(string filename, uint8_t *&raw_data,
uint64& uncompressed_trace_size)
{
// Read the trace file
// that the profiler can correctly set its start time to the unserialized
// value of curTick()
//
- clearStats();
- uint8* uncompressed_trace = NULL;
+ resetStats();
+ uint8_t *uncompressed_trace = NULL;
if (m_mem_vec_ptr != NULL) {
string memory_trace_file;
Sequencer* t = NULL;
for (int cntrl = 0; cntrl < m_abs_cntrl_vec.size(); cntrl++) {
sequencer_map.push_back(m_abs_cntrl_vec[cntrl]->getSequencer());
- if(t == NULL) t = sequencer_map[cntrl];
+ if (t == NULL) t = sequencer_map[cntrl];
}
assert(t != NULL);
Tick curtick_original = curTick();
// save the event queue head
Event* eventq_head = eventq->replaceHead(NULL);
- // set curTick to 0
+ // set curTick to 0 and reset Ruby System's clock
curTick(0);
+ resetClock();
// Schedule an event to start cache warmup
enqueueRubyEvent(curTick());
delete m_cache_recorder;
m_cache_recorder = NULL;
m_warmup_enabled = false;
+
// reset DRAM so that it's not waiting for events on the old event
// queue
- m_memory_controller->reset();
+ for (int i = 0; i < m_memory_controller_vec.size(); ++i) {
+ m_memory_controller_vec[i]->reset();
+ }
+
// Restore eventq head
eventq_head = eventq->replaceHead(eventq_head);
- // Restore curTick
+ // Restore curTick and Ruby System's clock
curTick(curtick_original);
+ resetClock();
}
}
}
void
-RubySystem::clearStats() const
+RubySystem::resetStats()
{
m_profiler_ptr->clearStats();
m_network_ptr->clearStats();
}
+bool
+RubySystem::functionalRead(PacketPtr pkt)
+{
+ Address address(pkt->getAddr());
+ Address line_address(address);
+ line_address.makeLineAddress();
+
+ AccessPermission access_perm = AccessPermission_NotPresent;
+ int num_controllers = m_abs_cntrl_vec.size();
+
+ DPRINTF(RubySystem, "Functional Read request for %s\n",address);
+
+ unsigned int num_ro = 0;
+ unsigned int num_rw = 0;
+ unsigned int num_busy = 0;
+ unsigned int num_backing_store = 0;
+ unsigned int num_invalid = 0;
+
+ // In this loop we count the number of controllers that have the given
+ // address in read only, read write and busy states.
+ for (unsigned int i = 0; i < num_controllers; ++i) {
+ access_perm = m_abs_cntrl_vec[i]-> getAccessPermission(line_address);
+ if (access_perm == AccessPermission_Read_Only)
+ num_ro++;
+ else if (access_perm == AccessPermission_Read_Write)
+ num_rw++;
+ else if (access_perm == AccessPermission_Busy)
+ num_busy++;
+ else if (access_perm == AccessPermission_Backing_Store)
+ // See RubySlicc_Exports.sm for details, but Backing_Store is meant
+ // to represent blocks in memory *for Broadcast/Snooping protocols*,
+ // where memory has no idea whether it has an exclusive copy of data
+ // or not.
+ num_backing_store++;
+ else if (access_perm == AccessPermission_Invalid ||
+ access_perm == AccessPermission_NotPresent)
+ num_invalid++;
+ }
+ assert(num_rw <= 1);
+
+ uint8_t *data = pkt->getPtr<uint8_t>(true);
+ unsigned int size_in_bytes = pkt->getSize();
+ unsigned startByte = address.getAddress() - line_address.getAddress();
+
+ // This if case is meant to capture what happens in a Broadcast/Snoop
+ // protocol where the block does not exist in the cache hierarchy. You
+ // only want to read from the Backing_Store memory if there is no copy in
+ // the cache hierarchy, otherwise you want to try to read the RO or RW
+ // copies existing in the cache hierarchy (covered by the else statement).
+ // The reason is because the Backing_Store memory could easily be stale, if
+ // there are copies floating around the cache hierarchy, so you want to read
+ // it only if it's not in the cache hierarchy at all.
+ if (num_invalid == (num_controllers - 1) &&
+ num_backing_store == 1) {
+ DPRINTF(RubySystem, "only copy in Backing_Store memory, read from it\n");
+ for (unsigned int i = 0; i < num_controllers; ++i) {
+ access_perm = m_abs_cntrl_vec[i]->getAccessPermission(line_address);
+ if (access_perm == AccessPermission_Backing_Store) {
+ DataBlock& block = m_abs_cntrl_vec[i]->
+ getDataBlock(line_address);
+
+ DPRINTF(RubySystem, "reading from %s block %s\n",
+ m_abs_cntrl_vec[i]->name(), block);
+ for (unsigned i = 0; i < size_in_bytes; ++i) {
+ data[i] = block.getByte(i + startByte);
+ }
+ return true;
+ }
+ }
+ } else if (num_ro > 0 || num_rw == 1) {
+ // In Broadcast/Snoop protocols, this covers if you know the block
+ // exists somewhere in the caching hierarchy, then you want to read any
+ // valid RO or RW block. In directory protocols, same thing, you want
+ // to read any valid readable copy of the block.
+ DPRINTF(RubySystem, "num_busy = %d, num_ro = %d, num_rw = %d\n",
+ num_busy, num_ro, num_rw);
+ // In this loop, we try to figure which controller has a read only or
+ // a read write copy of the given address. Any valid copy would suffice
+ // for a functional read.
+ for (unsigned int i = 0;i < num_controllers;++i) {
+ access_perm = m_abs_cntrl_vec[i]->getAccessPermission(line_address);
+ if (access_perm == AccessPermission_Read_Only ||
+ access_perm == AccessPermission_Read_Write) {
+ DataBlock& block = m_abs_cntrl_vec[i]->
+ getDataBlock(line_address);
+
+ DPRINTF(RubySystem, "reading from %s block %s\n",
+ m_abs_cntrl_vec[i]->name(), block);
+ for (unsigned i = 0; i < size_in_bytes; ++i) {
+ data[i] = block.getByte(i + startByte);
+ }
+ return true;
+ }
+ }
+ }
+
+ // Since we are here, this means that none of the controllers hold this
+ // address in a stable/base state. The function searches through all the
+ // buffers that exist in different cache, directory and memory
+ // controllers, and in the network components and reads the data portion
+ // of the first message that holds address specified in the packet.
+ for (unsigned int i = 0; i < num_controllers;++i) {
+ if (m_abs_cntrl_vec[i]->functionalReadBuffers(pkt)) {
+ return true;
+ }
+ }
+
+ for (unsigned int i = 0; i < m_memory_controller_vec.size(); ++i) {
+ if (m_memory_controller_vec[i]->functionalReadBuffers(pkt)) {
+ return true;
+ }
+ }
+
+ if (m_network_ptr->functionalRead(pkt)) {
+ return true;
+ }
+ return false;
+}
+
+// The function searches through all the buffers that exist in different
+// cache, directory and memory controllers, and in the network components
+// and writes the data portion of those that hold the address specified
+// in the packet.
+bool
+RubySystem::functionalWrite(PacketPtr pkt)
+{
+ Address addr(pkt->getAddr());
+ Address line_addr = line_address(addr);
+ AccessPermission access_perm = AccessPermission_NotPresent;
+ int num_controllers = m_abs_cntrl_vec.size();
+
+ DPRINTF(RubySystem, "Functional Write request for %s\n",addr);
+
+ uint8_t *data = pkt->getPtr<uint8_t>(true);
+ unsigned int size_in_bytes = pkt->getSize();
+ unsigned startByte = addr.getAddress() - line_addr.getAddress();
+
+ for (unsigned int i = 0; i < num_controllers;++i) {
+ m_abs_cntrl_vec[i]->functionalWriteBuffers(pkt);
+
+ access_perm = m_abs_cntrl_vec[i]->getAccessPermission(line_addr);
+ if (access_perm != AccessPermission_Invalid &&
+ access_perm != AccessPermission_NotPresent) {
+
+ DataBlock& block = m_abs_cntrl_vec[i]->getDataBlock(line_addr);
+ DPRINTF(RubySystem, "%s\n",block);
+ for (unsigned i = 0; i < size_in_bytes; ++i) {
+ block.setByte(i + startByte, data[i]);
+ }
+ DPRINTF(RubySystem, "%s\n",block);
+ }
+ }
+
+ uint32_t M5_VAR_USED num_functional_writes = 0;
+ for (unsigned int i = 0; i < m_memory_controller_vec.size() ;++i) {
+ num_functional_writes +=
+ m_memory_controller_vec[i]->functionalWriteBuffers(pkt);
+ }
+
+ num_functional_writes += m_network_ptr->functionalWrite(pkt);
+ DPRINTF(RubySystem, "Messages written = %u\n", num_functional_writes);
+
+ return true;
+}
+
#ifdef CHECK_COHERENCE
// This code will check for cases if the given cache block is exclusive in
// one node and shared in another-- a coherence violation
WARN_EXPR(exclusive);
WARN_EXPR(m_chip_vector[i]->getID());
WARN_EXPR(addr);
- WARN_EXPR(g_eventQueue_ptr->getTime());
+ WARN_EXPR(getTime());
ERROR_MSG("Coherence Violation Detected -- 2 exclusive chips");
} else if (sharedDetected) {
WARN_EXPR(lastShared);
WARN_EXPR(m_chip_vector[i]->getID());
WARN_EXPR(addr);
- WARN_EXPR(g_eventQueue_ptr->getTime());
+ WARN_EXPR(getTime());
ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
} else {
exclusive = m_chip_vector[i]->getID();
WARN_EXPR(lastShared);
WARN_EXPR(exclusive);
WARN_EXPR(addr);
- WARN_EXPR(g_eventQueue_ptr->getTime());
+ WARN_EXPR(getTime());
ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
}
}
* queue is executed.
*/
void
-RubyExitCallback::process()
+RubyDumpStatsCallback::process()
{
- std::ostream *os = simout.create(stats_filename);
- RubySystem::printConfig(*os);
- *os << endl;
- RubySystem::printStats(*os);
+ ruby_system->printStats(*os);
}
projects / gem5.git / blobdiff