ruby: Replace Time with Cycles in SequencerMessage

[gem5.git] / src / mem / simple_dram.hh

diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index 373408c2a874c76c1a0fda46f38a791c1b14b0c2..d8f51a7454e6c1248b1d93566e22c2455b8cf664 100644 (file)
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -46,6 +46,8 @@
 #ifndef __MEM_SIMPLE_DRAM_HH__
 #define __MEM_SIMPLE_DRAM_HH__
 
+#include <deque>
+
 #include "base/statistics.hh"
 #include "enums/AddrMap.hh"
 #include "enums/MemSched.hh"
@@ -127,6 +129,9 @@ class SimpleDRAM : public AbstractMemory
      */
     bool stopReads;
 
+    /** List to keep track of activate ticks */
+    std::deque<Tick> actTicks;
+
     /**
      * A basic class to track the bank state indirectly via
      * times "freeAt" and "tRASDoneAt" and what page is currently open
@@ -323,6 +328,15 @@ class SimpleDRAM : public AbstractMemory
      */
     Tick maxBankFreeAt() const;
 
+
+    /**
+     * Keep track of when row activations happen, in order to enforce
+     * the maximum number of activations in the activation window. The
+     * method updates the time that the banks become available based
+     * on the current limits.
+     */
+    void recordActivate(Tick act_tick);
+
     void printParams() const;
     void printQs() const;
 
@@ -381,6 +395,8 @@ class SimpleDRAM : public AbstractMemory
     const Tick tRP;
     const Tick tRFC;
     const Tick tREFI;
+    const Tick tXAW;
+    const uint32_t activationLimit;
 
     /**
      * Memory controller configuration initialized based on parameter
@@ -453,6 +469,12 @@ class SimpleDRAM : public AbstractMemory
     Stats::Formula writeRowHitRate;
     Stats::Formula avgGap;
 
+    /** @todo this is a temporary workaround until the 4-phase code is
+     * committed. upstream caches needs this packet until true is returned, so
+     * hold onto it for deletion until a subsequent call
+     */
+    std::vector<PacketPtr> pendingDelete;
+
   public:
 
     void regStats();