#ifndef __MEM_SIMPLE_DRAM_HH__
#define __MEM_SIMPLE_DRAM_HH__
+#include <deque>
+
#include "base/statistics.hh"
#include "enums/AddrMap.hh"
#include "enums/MemSched.hh"
*/
bool stopReads;
+ /** List to keep track of activate ticks */
+ std::deque<Tick> actTicks;
+
/**
* A basic class to track the bank state indirectly via
* times "freeAt" and "tRASDoneAt" and what page is currently open
*/
Tick maxBankFreeAt() const;
+
+ /**
+ * Keep track of when row activations happen, in order to enforce
+ * the maximum number of activations in the activation window. The
+ * method updates the time that the banks become available based
+ * on the current limits.
+ */
+ void recordActivate(Tick act_tick);
+
void printParams() const;
void printQs() const;
*/
std::list<DRAMPacket*> dramRespQueue;
- /** If we need to drain, keep the drain event around until we're done
+ /** If we need to drain, keep the drain manager around until we're done
* here.
*/
- Event *drainEvent;
+ DrainManager *drainManager;
/**
* Multi-dimensional vector of banks, first dimension is ranks,
const Tick tRP;
const Tick tRFC;
const Tick tREFI;
+ const Tick tXAW;
+ const uint32_t activationLimit;
/**
* Memory controller configuration initialized based on parameter
Stats::Formula writeRowHitRate;
Stats::Formula avgGap;
+ /** @todo this is a temporary workaround until the 4-phase code is
+ * committed. upstream caches needs this packet until true is returned, so
+ * hold onto it for deletion until a subsequent call
+ */
+ std::vector<PacketPtr> pendingDelete;
+
public:
void regStats();
SimpleDRAM(const SimpleDRAMParams* p);
- unsigned int drain(Event* de);
+ unsigned int drain(DrainManager* dm);
- virtual SlavePort& getSlavePort(const std::string& if_name,
- int idx = InvalidPortID);
+ virtual BaseSlavePort& getSlavePort(const std::string& if_name,
+ PortID idx = InvalidPortID);
virtual void init();
virtual void startup();