/*
- * Copyright (c) 2010-2013 ARM Limited
+ * Copyright (c) 2010-2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ron Dreslinski
- * Ali Saidi
- * Andreas Hansson
*/
-#include "base/random.hh"
#include "mem/simple_mem.hh"
-#include "debug/Drain.hh"
-using namespace std;
+#include "base/random.hh"
+#include "base/trace.hh"
+#include "debug/Drain.hh"
-SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
+SimpleMemory::SimpleMemory(const SimpleMemoryParams &p) :
AbstractMemory(p),
- port(name() + ".port", *this), latency(p->latency),
- latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
+ port(name() + ".port", *this), latency(p.latency),
+ latency_var(p.latency_var), bandwidth(p.bandwidth), isBusy(false),
retryReq(false), retryResp(false),
- releaseEvent(this), dequeueEvent(this)
+ releaseEvent([this]{ release(); }, name()),
+ dequeueEvent([this]{ dequeue(); }, name())
{
}
Tick
SimpleMemory::recvAtomic(PacketPtr pkt)
{
+ panic_if(pkt->cacheResponding(), "Should not see packets where cache "
+ "is responding");
+
access(pkt);
- return pkt->memInhibitAsserted() ? 0 : getLatency();
+ return getLatency();
+}
+
+Tick
+SimpleMemory::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
+{
+ Tick latency = recvAtomic(pkt);
+ getBackdoor(_backdoor);
+ return latency;
}
void
auto p = packetQueue.begin();
// potentially update the packets in our packet queue as well
while (!done && p != packetQueue.end()) {
- done = pkt->checkFunctional(p->pkt);
+ done = pkt->trySatisfyFunctional(p->pkt);
++p;
}
bool
SimpleMemory::recvTimingReq(PacketPtr pkt)
{
- if (pkt->memInhibitAsserted()) {
- // snooper will supply based on copy of packet
- // still target's responsibility to delete packet
- pendingDelete.reset(pkt);
- return true;
- }
+ panic_if(pkt->cacheResponding(), "Should not see packets where cache "
+ "is responding");
+
+ panic_if(!(pkt->isRead() || pkt->isWrite()),
+ "Should only see read and writes at memory controller, "
+ "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
- // we should never get a new request after committing to retry the
- // current one, the bus violates the rule as it simply sends a
- // retry to the next one waiting on the retry list, so simply
- // ignore it
+ // we should not get a new request after committing to retry the
+ // current one, but unfortunately the CPU violates this rule, so
+ // simply ignore it for now
if (retryReq)
return false;
return false;
}
- // @todo someone should pay for this
+ // technically the packet only reaches us after the header delay,
+ // and since this is a memory controller we also need to
+ // deserialise the payload before performing any write operation
+ Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
// update the release time according to the bandwidth limit, and
// rather than long term as it is the short term data rate that is
// limited for any real memory
- // only look at reads and writes when determining if we are busy,
- // and for how long, as it is not clear what to regulate for the
- // other types of commands
- if (pkt->isRead() || pkt->isWrite()) {
- // calculate an appropriate tick to release to not exceed
- // the bandwidth limit
- Tick duration = pkt->getSize() * bandwidth;
-
- // only consider ourselves busy if there is any need to wait
- // to avoid extra events being scheduled for (infinitely) fast
- // memories
- if (duration != 0) {
- schedule(releaseEvent, curTick() + duration);
- isBusy = true;
- }
+ // calculate an appropriate tick to release to not exceed
+ // the bandwidth limit
+ Tick duration = pkt->getSize() * bandwidth;
+
+ // only consider ourselves busy if there is any need to wait
+ // to avoid extra events being scheduled for (infinitely) fast
+ // memories
+ if (duration != 0) {
+ schedule(releaseEvent, curTick() + duration);
+ isBusy = true;
}
// go ahead and deal with the packet and put the response in the
// queue if there is one
bool needsResponse = pkt->needsResponse();
recvAtomic(pkt);
- // turn packet around to go back to requester if response expected
+ // turn packet around to go back to requestor if response expected
if (needsResponse) {
// recvAtomic() should already have turned packet into
// atomic response
assert(pkt->isResponse());
- // to keep things simple (and in order), we put the packet at
- // the end even if the latency suggests it should be sent
- // before the packet(s) before it
- packetQueue.emplace_back(pkt, curTick() + getLatency());
+
+ Tick when_to_send = curTick() + receive_delay + getLatency();
+
+ // typically this should be added at the end, so start the
+ // insertion sort with the last element, also make sure not to
+ // re-order in front of some existing packet with the same
+ // address, the latter is important as this memory effectively
+ // hands out exclusive copies (shared is not asserted)
+ auto i = packetQueue.end();
+ --i;
+ while (i != packetQueue.begin() && when_to_send < i->tick &&
+ !i->pkt->matchAddr(pkt))
+ --i;
+
+ // emplace inserts the element before the position pointed to by
+ // the iterator, so advance it one step
+ packetQueue.emplace(++i, pkt, when_to_send);
+
if (!retryResp && !dequeueEvent.scheduled())
schedule(dequeueEvent, packetQueue.back().tick);
} else {
dequeue();
}
-BaseSlavePort &
-SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+SimpleMemory::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getSlavePort(if_name, idx);
+ return AbstractMemory::getPort(if_name, idx);
} else {
return port;
}
SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
SimpleMemory& _memory)
- : SlavePort(_name, &_memory), memory(_memory)
+ : ResponsePort(_name, &_memory), memory(_memory)
{ }
AddrRangeList
return memory.recvAtomic(pkt);
}
+Tick
+SimpleMemory::MemoryPort::recvAtomicBackdoor(
+ PacketPtr pkt, MemBackdoorPtr &_backdoor)
+{
+ return memory.recvAtomicBackdoor(pkt, _backdoor);
+}
+
void
SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
{
{
memory.recvRespRetry();
}
-
-SimpleMemory*
-SimpleMemoryParams::create()
-{
- return new SimpleMemory(this);
-}
projects / gem5.git / blobdiff