cpu: Apply the ARM TLB rework to the O3 checker CPU.

[gem5.git] / src / mem / simple_mem.cc

diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 32fea1e89082d9703960b0ed97d977f71562bb8f..9e7dfc815bf1821f3fa9788ab247cc442c185030 100644 (file)
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -80,6 +80,16 @@ SimpleMemory::recvAtomic(PacketPtr pkt)
     return getLatency();
 }
 
+Tick
+SimpleMemory::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
+{
+    Tick latency = recvAtomic(pkt);
+
+    if (backdoor.ptr())
+        _backdoor = &backdoor;
+    return latency;
+}
+
 void
 SimpleMemory::recvFunctional(PacketPtr pkt)
 {
@@ -164,7 +174,7 @@ SimpleMemory::recvTimingReq(PacketPtr pkt)
         auto i = packetQueue.end();
         --i;
         while (i != packetQueue.begin() && when_to_send < i->tick &&
-               i->pkt->getAddr() != pkt->getAddr())
+               !i->pkt->matchAddr(pkt))
             --i;
 
         // emplace inserts the element before the position pointed to by
@@ -235,7 +245,7 @@ Port &
 SimpleMemory::getPort(const std::string &if_name, PortID idx)
 {
     if (if_name != "port") {
-        return MemObject::getPort(if_name, idx);
+        return AbstractMemory::getPort(if_name, idx);
     } else {
         return port;
     }
@@ -271,6 +281,13 @@ SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
     return memory.recvAtomic(pkt);
 }
 
+Tick
+SimpleMemory::MemoryPort::recvAtomicBackdoor(
+        PacketPtr pkt, MemBackdoorPtr &_backdoor)
+{
+    return memory.recvAtomicBackdoor(pkt, _backdoor);
+}
+
 void
 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 {