* SimpleMemory declaration
*/
-#ifndef __SIMPLE_MEMORY_HH__
-#define __SIMPLE_MEMORY_HH__
+#ifndef __MEM_SIMPLE_MEMORY_HH__
+#define __MEM_SIMPLE_MEMORY_HH__
-#include <deque>
+#include <list>
#include "mem/abstract_mem.hh"
#include "mem/port.hh"
* actual memory access. Note that this is where the packet spends
* the memory latency.
*/
- std::deque<DeferredPacket> packetQueue;
+ std::list<DeferredPacket> packetQueue;
/**
* Bandwidth in ticks per byte. The regulation affects the
*/
void release();
- EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
+ EventFunctionWrapper releaseEvent;
/**
* Dequeue a packet from our internal packet queue and move it to
*/
void dequeue();
- EventWrapper<SimpleMemory, &SimpleMemory::dequeue> dequeueEvent;
+ EventFunctionWrapper dequeueEvent;
/**
* Detemine the latency.
*/
Tick getLatency() const;
- /** @todo this is a temporary workaround until the 4-phase code is
- * committed. upstream caches needs this packet until true is returned, so
- * hold onto it for deletion until a subsequent call
- */
- std::vector<PacketPtr> pendingDelete;
-
/**
- * If we need to drain, keep the drain manager around until we're
- * done here.
+ * Upstream caches need this packet until true is returned, so
+ * hold it for deletion until a subsequent call
*/
- DrainManager *drainManager;
+ std::unique_ptr<Packet> pendingDelete;
public:
SimpleMemory(const SimpleMemoryParams *p);
- unsigned int drain(DrainManager *dm);
+ DrainState drain() override;
BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
- void init();
+ PortID idx = InvalidPortID) override;
+ void init() override;
protected:
};
-#endif //__SIMPLE_MEMORY_HH__
+#endif //__MEM_SIMPLE_MEMORY_HH__