ruby: handle llsc accesses through CacheEntry, not CacheMemory

[gem5.git] / src / mem / simple_mem.hh

diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index ba4b8bdf12171ad3da360236f51eac61fbeb8277..98c41623f3500e5364f03501a0473f3be2c059db 100644 (file)
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -101,7 +101,7 @@ class SimpleMemory : public AbstractMemory
 
         bool recvTimingReq(PacketPtr pkt);
 
-        void recvRetry();
+        void recvRespRetry();
 
         AddrRangeList getAddrRanges() const;
 
@@ -181,17 +181,11 @@ class SimpleMemory : public AbstractMemory
      */
     std::vector<PacketPtr> pendingDelete;
 
-    /**
-     * If we need to drain, keep the drain manager around until we're
-     * done here.
-     */
-    DrainManager *drainManager;
-
   public:
 
     SimpleMemory(const SimpleMemoryParams *p);
 
-    unsigned int drain(DrainManager *dm);
+    DrainState drain() M5_ATTR_OVERRIDE;
 
     BaseSlavePort& getSlavePort(const std::string& if_name,
                                 PortID idx = InvalidPortID);
@@ -205,7 +199,7 @@ class SimpleMemory : public AbstractMemory
 
     bool recvTimingReq(PacketPtr pkt);
 
-    void recvRetry();
+    void recvRespRetry();
 
 };