* an configurable throughput and latency, potentially with a variance
* added to the latter. It uses a QueueSlavePort to avoid dealing with
* the flow control of sending responses.
+ * @sa \ref gem5MemorySystem "gem5 Memory System"
*/
class SimpleMemory : public AbstractMemory
{
EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
+ /** @todo this is a temporary workaround until the 4-phase code is
+ * committed. upstream caches needs this packet until true is returned, so
+ * hold onto it for deletion until a subsequent call
+ */
+ std::vector<PacketPtr> pendingDelete;
+
public:
SimpleMemory(const SimpleMemoryParams *p);
virtual ~SimpleMemory() { }
- unsigned int drain(Event* de);
+ unsigned int drain(DrainManager *dm);
- virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
+ virtual BaseSlavePort& getSlavePort(const std::string& if_name,
+ PortID idx = InvalidPortID);
virtual void init();
protected: