mem: Fix guest corruption when caches handle uncacheable accesses

[gem5.git] / src / mem / simple_mem.hh

diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 4f7af864b8fd21a6fa61b37148505dae22b42771..ab002f2702f7fc7af24f51692f0fb0be27ade462 100644 (file)
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -58,6 +58,7 @@
  * an configurable throughput and latency, potentially with a variance
  * added to the latter. It uses a QueueSlavePort to avoid dealing with
  * the flow control of sending responses.
+ * @sa  \ref gem5MemorySystem "gem5 Memory System"
  */
 class SimpleMemory : public AbstractMemory
 {
@@ -117,14 +118,21 @@ class SimpleMemory : public AbstractMemory
 
     EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
 
+    /** @todo this is a temporary workaround until the 4-phase code is
+     * committed. upstream caches needs this packet until true is returned, so
+     * hold onto it for deletion until a subsequent call
+     */
+    std::vector<PacketPtr> pendingDelete;
+
   public:
 
     SimpleMemory(const SimpleMemoryParams *p);
     virtual ~SimpleMemory() { }
 
-    unsigned int drain(Event* de);
+    unsigned int drain(DrainManager *dm);
 
-    virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
+    virtual BaseSlavePort& getSlavePort(const std::string& if_name,
+                                        PortID idx = InvalidPortID);
     virtual void init();
 
   protected: