"WireBuffer": "RubyWireBuffer",
"Sequencer": "RubySequencer",
"DirectoryMemory": "RubyDirectoryMemory",
- "MemoryControl": "RubyMemoryControl",
+ "MemoryControl": "MemoryControl",
"DMASequencer": "DMASequencer"
}
self.printProfileDumperCC(path)
self.printProfileDumperHH(path)
- for func in self.functions:
- func.writeCodeFiles(path)
-
def printControllerPython(self, path):
code = self.symtab.codeFormatter()
ident = self.ident
const int & getVersion() const;
const std::string toString() const;
const std::string getName() const;
- const MachineType getMachineType() const;
void stallBuffer(MessageBuffer* buf, Address addr);
void wakeUpBuffers(Address addr);
void wakeUpAllBuffers();
void clearStats();
void blockOnQueue(Address addr, MessageBuffer* port);
void unblock(Address addr);
+ void recordCacheTrace(int cntrl, CacheRecorder* tr);
+ Sequencer* getSequencer() const;
private:
''')
bool m_is_blocking;
std::map<Address, MessageBuffer*> m_block_map;
typedef std::vector<MessageBuffer*> MsgVecType;
-typedef m5::hash_map< Address, MsgVecType* > WaitingBufType;
+typedef std::map< Address, MsgVecType* > WaitingBufType;
WaitingBufType m_waiting_buffers;
int m_max_in_port_rank;
int m_cur_in_port_rank;
// Set and Reset for cache_entry variable
void set_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, AbstractCacheEntry* m_new_cache_entry);
void unset_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr);
-// Set permissions for the cache_entry
-void set_permission(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, AccessPermission perm);
''')
if self.TBEType != None:
* Created by slicc definition of Module "${{self.short}}"
*/
+#include <sys/types.h>
+#include <unistd.h>
+
#include <cassert>
#include <sstream>
#include <string>
+#include "base/compiler.hh"
#include "base/cprintf.hh"
#include "debug/RubyGenerated.hh"
#include "debug/RubySlicc.hh"
m_recycle_latency = p->recycle_latency;
m_number_of_TBEs = p->number_of_TBEs;
m_is_blocking = false;
+ m_name = "${ident}";
''')
#
# max_port_rank is used to size vectors and thus should be one plus the
code('''
m_${{seq}}_ptr->setController(this);
''')
+
+ else:
+ for seq in sequencers:
+ code('''
+m_${{seq}}_ptr->setController(this);
+ ''')
+
#
# For the DMA controller, pass the sequencer a pointer to the
# controller.
network = var["network"]
ordered = var["ordered"]
vnet = var["virtual_network"]
+ vnet_type = var["vnet_type"]
assert var.machine is not None
code('''
machine_type = string_to_MachineType("${{var.machine.ident}}");
base = MachineType_base_number(machine_type);
-$vid = m_net_ptr->get${network}NetQueue(m_version + base, $ordered, $vnet);
+$vid = m_net_ptr->get${network}NetQueue(m_version + base, $ordered, $vnet, "$vnet_type");
''')
code('assert($vid != NULL);')
else:
mq_ident = "NULL"
+ seq_ident = "NULL"
+ for param in self.config_parameters:
+ if param.name == "sequencer":
+ assert(param.pointer)
+ seq_ident = "m_%s_ptr" % param.name
+
code('''
int
$c_ident::getNumControllers()
return $mq_ident;
}
+Sequencer*
+$c_ident::getSequencer() const
+{
+ return $seq_ident;
+}
+
const int &
$c_ident::getVersion() const
{
return m_name;
}
-const MachineType
-$c_ident::getMachineType() const
-{
- return MachineType_${ident};
-}
-
void
$c_ident::stallBuffer(MessageBuffer* buf, Address addr)
{
{
m_cache_entry_ptr = 0;
}
-
-void
-$c_ident::set_permission(${{self.EntryType.c_ident}}*& m_cache_entry_ptr,
- AccessPermission perm)
-{
- if (m_cache_entry_ptr != NULL) {
- m_cache_entry_ptr->changePermission(perm);
- }
-}
''')
if self.TBEType != None:
code('''
+void
+$c_ident::recordCacheTrace(int cntrl, CacheRecorder* tr)
+{
+''')
+ #
+ # Record cache contents for all associated caches.
+ #
+ code.indent()
+ for param in self.config_parameters:
+ if param.type_ast.type.ident == "CacheMemory":
+ assert(param.pointer)
+ code('m_${{param.ident}}_ptr->recordCacheContents(cntrl, tr);')
+
+ code.dedent()
+ code('''
+}
+
// Actions
''')
if self.TBEType != None and self.EntryType != None:
}
''')
+ for func in self.functions:
+ code(func.generateCode())
+
code.write(path, "%s.cc" % c_ident)
def printCWakeup(self, path):
// Auto generated C++ code started by $__file__:$__line__
// ${ident}: ${{self.short}}
+#include <sys/types.h>
+#include <unistd.h>
+
#include <cassert>
#include "base/misc.hh"
{
''')
if self.TBEType != None and self.EntryType != None:
- code('${ident}_State state = ${ident}_getState(m_tbe_ptr, m_cache_entry_ptr, addr);')
+ code('${ident}_State state = getState(m_tbe_ptr, m_cache_entry_ptr, addr);')
elif self.TBEType != None:
- code('${ident}_State state = ${ident}_getState(m_tbe_ptr, addr);')
+ code('${ident}_State state = getState(m_tbe_ptr, addr);')
elif self.EntryType != None:
- code('${ident}_State state = ${ident}_getState(m_cache_entry_ptr, addr);')
+ code('${ident}_State state = getState(m_cache_entry_ptr, addr);')
else:
- code('${ident}_State state = ${ident}_getState(addr);')
+ code('${ident}_State state = getState(addr);')
code('''
${ident}_State next_state = state;
CLEAR_TRANSITION_COMMENT();
''')
if self.TBEType != None and self.EntryType != None:
- code('${ident}_setState(m_tbe_ptr, m_cache_entry_ptr, addr, next_state);')
- code('set_permission(m_cache_entry_ptr, ${ident}_State_to_permission(next_state));')
+ code('setState(m_tbe_ptr, m_cache_entry_ptr, addr, next_state);')
+ code('setAccessPermission(m_cache_entry_ptr, addr, next_state);')
elif self.TBEType != None:
- code('${ident}_setState(m_tbe_ptr, addr, next_state);')
+ code('setState(m_tbe_ptr, addr, next_state);')
+ code('setAccessPermission(addr, next_state);')
elif self.EntryType != None:
- code('${ident}_setState(m_cache_entry_ptr, addr, next_state);')
- code('set_permission(m_cache_entry_ptr, ${ident}_State_to_permission(next_state));')
+ code('setState(m_cache_entry_ptr, addr, next_state);')
+ code('setAccessPermission(m_cache_entry_ptr, addr, next_state);')
else:
- code('${ident}_setState(addr, next_state);')
+ code('setState(addr, next_state);')
+ code('setAccessPermission(addr, next_state);')
code('''
} else if (result == TransitionResult_ResourceStall) {
#include "mem/protocol/${ident}_Event.hh"
#include "mem/protocol/${ident}_State.hh"
-#include "mem/ruby/common/Global.hh"
+#include "mem/ruby/common/TypeDefines.hh"
class ${ident}_Profiler
{