ruby: memory controllers now inherit from an abstract "MemoryControl" class

[gem5.git] / src / mem / slicc / symbols / StateMachine.py

diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index a3ea1ca8adb7113aedafc36ddcbe757a7b27677a..8f4676c4221e76c261bf3127f6353b81fe7b3768 100644 (file)
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -39,7 +39,7 @@ python_class_map = {"int": "Int",
                     "WireBuffer": "RubyWireBuffer",
                     "Sequencer": "RubySequencer",
                     "DirectoryMemory": "RubyDirectoryMemory",
-                    "MemoryControl": "RubyMemoryControl",
+                    "MemoryControl": "MemoryControl",
                     "DMASequencer": "DMASequencer"
                     }
 
@@ -264,6 +264,8 @@ public:
     void clearStats();
     void blockOnQueue(Address addr, MessageBuffer* port);
     void unblock(Address addr);
+    void recordCacheTrace(int cntrl, CacheRecorder* tr);
+    Sequencer* getSequencer() const;
 
 private:
 ''')
@@ -322,7 +324,7 @@ MachineID m_machineID;
 bool m_is_blocking;
 std::map<Address, MessageBuffer*> m_block_map;
 typedef std::vector<MessageBuffer*> MsgVecType;
-typedef m5::hash_map< Address, MsgVecType* > WaitingBufType;
+typedef std::map< Address, MsgVecType* > WaitingBufType;
 WaitingBufType m_waiting_buffers;
 int m_max_in_port_rank;
 int m_cur_in_port_rank;
@@ -406,6 +408,9 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
  * Created by slicc definition of Module "${{self.short}}"
  */
 
+#include <sys/types.h>
+#include <unistd.h>
+
 #include <cassert>
 #include <sstream>
 #include <string>
@@ -497,6 +502,13 @@ $c_ident::$c_ident(const Params *p)
                 code('''
 m_${{seq}}_ptr->setController(this);
     ''')
+
+        else:
+            for seq in sequencers:
+                code('''
+m_${{seq}}_ptr->setController(this);
+    ''')
+
         #
         # For the DMA controller, pass the sequencer a pointer to the
         # controller.
@@ -674,6 +686,12 @@ $vid->setDescription("[Version " + to_string(m_version) + ", ${ident}, name=${{v
         else:
             mq_ident = "NULL"
 
+        seq_ident = "NULL"
+        for param in self.config_parameters:
+            if param.name == "sequencer":
+                assert(param.pointer)
+                seq_ident = "m_%s_ptr" % param.name
+
         code('''
 int
 $c_ident::getNumControllers()
@@ -687,6 +705,12 @@ $c_ident::getMandatoryQueue() const
     return $mq_ident;
 }
 
+Sequencer*
+$c_ident::getSequencer() const
+{
+    return $seq_ident;
+}
+
 const int &
 $c_ident::getVersion() const
 {
@@ -875,6 +899,23 @@ $c_ident::unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr)
 
         code('''
 
+void
+$c_ident::recordCacheTrace(int cntrl, CacheRecorder* tr)
+{
+''')
+        #
+        # Record cache contents for all associated caches.
+        #
+        code.indent()
+        for param in self.config_parameters:
+            if param.type_ast.type.ident == "CacheMemory":
+                assert(param.pointer)
+                code('m_${{param.ident}}_ptr->recordCacheContents(cntrl, tr);')
+
+        code.dedent()
+        code('''
+}
+
 // Actions
 ''')
         if self.TBEType != None and self.EntryType != None:
@@ -952,6 +993,9 @@ $c_ident::${{action.ident}}(const Address& addr)
 // Auto generated C++ code started by $__file__:$__line__
 // ${ident}: ${{self.short}}
 
+#include <sys/types.h>
+#include <unistd.h>
+
 #include <cassert>
 
 #include "base/misc.hh"