void print(std::ostream& out) const;
void wakeup();
- void printStats(std::ostream& out) const;
- void clearStats();
+ void resetStats();
void regStats();
void collateStats();
''')
code('''
- const Address& addr);
+ const Address addr);
TransitionResult doTransitionWorker(${ident}_Event event,
${ident}_State state,
void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
''')
+ # Prototype the actions that the controller can take
code('''
// Actions
if self.TBEType != None and self.EntryType != None:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
- code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, ${{self.EntryType.c_ident}}*& m_cache_entry_ptr, const Address& addr);')
+ code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& '
+ 'm_tbe_ptr, ${{self.EntryType.c_ident}}*& '
+ 'm_cache_entry_ptr, const Address& addr);')
elif self.TBEType != None:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
- code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, const Address& addr);')
+ code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& '
+ 'm_tbe_ptr, const Address& addr);')
elif self.EntryType != None:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
- code('void ${{action.ident}}(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, const Address& addr);')
+ code('void ${{action.ident}}(${{self.EntryType.c_ident}}*& '
+ 'm_cache_entry_ptr, const Address& addr);')
else:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
code('#include "mem/protocol/${{var.type.c_ident}}.hh"')
seen_types.add(var.type.ident)
+ num_in_ports = len(self.in_ports)
+
code('''
$c_ident *
${c_ident}Params::create()
$c_ident::$c_ident(const Params *p)
: AbstractController(p)
{
- m_name = "${ident}";
+ m_machineID.type = MachineType_${ident};
+ m_machineID.num = m_version;
+ m_num_controllers++;
+
+ m_in_ports = $num_in_ports;
''')
- #
- # max_port_rank is used to size vectors and thus should be one plus the
- # largest port rank
- #
- max_port_rank = self.in_ports[0].pairs["max_port_rank"] + 1
- code(' m_max_in_port_rank = $max_port_rank;')
code.indent()
#
# After initializing the universal machine parameters, initialize the
- # this machines config parameters. Also detemine if these configuration
- # params include a sequencer. This information will be used later for
- # contecting the sequencer back to the L1 cache controller.
+ # this machines config parameters. Also if these configuration params
+ # include a sequencer, connect the it to the controller.
#
- contains_dma_sequencer = False
- sequencers = []
for param in self.config_parameters:
- if param.name == "dma_sequencer":
- contains_dma_sequencer = True
- elif re.compile("sequencer").search(param.name):
- sequencers.append(param.name)
if param.pointer:
code('m_${{param.name}}_ptr = p->${{param.name}};')
else:
code('m_${{param.name}} = p->${{param.name}};')
-
- #
- # For the l1 cache controller, add the special atomic support which
- # includes passing the sequencer a pointer to the controller.
- #
- for seq in sequencers:
- code('''
-m_${{seq}}_ptr->setController(this);
- ''')
-
- #
- # For the DMA controller, pass the sequencer a pointer to the
- # controller.
- #
- if self.ident == "DMA":
- if not contains_dma_sequencer:
- self.error("The DMA controller must include the sequencer " \
- "configuration parameter")
-
- code('''
-m_dma_sequencer_ptr->setController(this);
-''')
+ if re.compile("sequencer").search(param.name):
+ code('m_${{param.name}}_ptr->setController(this);')
- code('m_num_controllers++;')
for var in self.objects:
if var.ident.find("mandatoryQueue") >= 0:
code('''
$c_ident::init()
{
MachineType machine_type = string_to_MachineType("${{var.machine.ident}}");
- int base = MachineType_base_number(machine_type);
-
- m_machineID.type = MachineType_${ident};
- m_machineID.num = m_version;
+ int base M5_VAR_USED = MachineType_base_number(machine_type);
// initialize objects
code.dedent()
code('''
AbstractController::init();
- clearStats();
+ resetStats();
}
''')
- has_mandatory_q = False
+ mq_ident = "NULL"
for port in self.in_ports:
if port.code.find("mandatoryQueue_ptr") >= 0:
- has_mandatory_q = True
-
- if has_mandatory_q:
- mq_ident = "m_%s_mandatoryQueue_ptr" % self.ident
- else:
- mq_ident = "NULL"
+ mq_ident = "m_%s_mandatoryQueue_ptr" % self.ident
seq_ident = "NULL"
for param in self.config_parameters:
void
$c_ident::regStats()
{
+ AbstractController::regStats();
+
if (m_version == 0) {
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
Stats::Vector *t = new Stats::Vector();
t->init(m_num_controllers);
- t->name(name() + "." + ${ident}_Event_to_string(event));
+ t->name(g_system_ptr->name() + ".${c_ident}." +
+ ${ident}_Event_to_string(event));
t->flags(Stats::pdf | Stats::total | Stats::oneline |
Stats::nozero);
Stats::Vector *t = new Stats::Vector();
t->init(m_num_controllers);
- t->name(name() + "." + ${ident}_State_to_string(state) +
+ t->name(g_system_ptr->name() + ".${c_ident}." +
+ ${ident}_State_to_string(state) +
"." + ${ident}_Event_to_string(event));
t->flags(Stats::pdf | Stats::total | Stats::oneline |
out << "[$c_ident " << m_version << "]";
}
-void
-$c_ident::printStats(ostream& out) const
-{
-''')
- #
- # Cache and Memory Controllers have specific profilers associated with
- # them. Print out these stats before dumping state transition stats.
- #
- for param in self.config_parameters:
- if param.type_ast.type.ident == "DirectoryMemory":
- assert(param.pointer)
- code(' m_${{param.ident}}_ptr->printStats(out);')
-
- code('''
-}
-
-void $c_ident::clearStats()
+void $c_ident::resetStats()
{
for (int state = 0; state < ${ident}_State_NUM; state++) {
for (int event = 0; event < ${ident}_Event_NUM; event++) {
m_event_counters[event] = 0;
}
- AbstractController::clearStats();
+ AbstractController::resetStats();
}
''')
code.indent()
code('// ${ident}InPort $port')
if port.pairs.has_key("rank"):
- code('m_cur_in_port_rank = ${{port.pairs["rank"]}};')
+ code('m_cur_in_port = ${{port.pairs["rank"]}};')
else:
- code('m_cur_in_port_rank = 0;')
+ code('m_cur_in_port = 0;')
code('${{port["c_code_in_port"]}}')
code.dedent()
${{self.TBEType.c_ident}}* m_tbe_ptr,
''')
code('''
- const Address &addr)
+ const Address addr)
{
''')
if self.TBEType != None and self.EntryType != None:
projects / gem5.git / blobdiff