ruby: slicc: code refactor
[gem5.git] / src / mem / slicc / symbols / StateMachine.py
index 89bb5dc0a5b364b6a58cf948a5595a134ad58a37..d908f00c6b50542386f4246fc5008262a004a833 100644 (file)
@@ -257,7 +257,7 @@ class $c_ident : public AbstractController
 
     void print(std::ostream& out) const;
     void wakeup();
-    void clearStats();
+    void resetStats();
     void regStats();
     void collateStats();
 
@@ -351,6 +351,7 @@ void set_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr, ${ident}_TBE* m_new_tbe);
 void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
 ''')
 
+        # Prototype the actions that the controller can take
         code('''
 
 // Actions
@@ -358,15 +359,19 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
         if self.TBEType != None and self.EntryType != None:
             for action in self.actions.itervalues():
                 code('/** \\brief ${{action.desc}} */')
-                code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, ${{self.EntryType.c_ident}}*& m_cache_entry_ptr, const Address& addr);')
+                code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& '
+                     'm_tbe_ptr, ${{self.EntryType.c_ident}}*& '
+                     'm_cache_entry_ptr, const Address& addr);')
         elif self.TBEType != None:
             for action in self.actions.itervalues():
                 code('/** \\brief ${{action.desc}} */')
-                code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, const Address& addr);')
+                code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& '
+                     'm_tbe_ptr, const Address& addr);')
         elif self.EntryType != None:
             for action in self.actions.itervalues():
                 code('/** \\brief ${{action.desc}} */')
-                code('void ${{action.ident}}(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, const Address& addr);')
+                code('void ${{action.ident}}(${{self.EntryType.c_ident}}*& '
+                     'm_cache_entry_ptr, const Address& addr);')
         else:
             for action in self.actions.itervalues():
                 code('/** \\brief ${{action.desc}} */')
@@ -434,6 +439,8 @@ using namespace std;
                 code('#include "mem/protocol/${{var.type.c_ident}}.hh"')
             seen_types.add(var.type.ident)
 
+        num_in_ports = len(self.in_ports)
+
         code('''
 $c_ident *
 ${c_ident}Params::create()
@@ -458,53 +465,27 @@ stringstream ${ident}_transitionComment;
 $c_ident::$c_ident(const Params *p)
     : AbstractController(p)
 {
-    m_name = "${ident}";
+    m_machineID.type = MachineType_${ident};
+    m_machineID.num = m_version;
+    m_num_controllers++;
+
+    m_in_ports = $num_in_ports;
 ''')
-        num_in_ports = len(self.in_ports)
-        code('    m_in_ports = $num_in_ports;')
         code.indent()
 
         #
         # After initializing the universal machine parameters, initialize the
-        # this machines config parameters.  Also detemine if these configuration
-        # params include a sequencer.  This information will be used later for
-        # contecting the sequencer back to the L1 cache controller.
+        # this machines config parameters.  Also if these configuration params
+        # include a sequencer, connect the it to the controller.
         #
-        contains_dma_sequencer = False
-        sequencers = []
         for param in self.config_parameters:
-            if param.name == "dma_sequencer":
-                contains_dma_sequencer = True
-            elif re.compile("sequencer").search(param.name):
-                sequencers.append(param.name)
             if param.pointer:
                 code('m_${{param.name}}_ptr = p->${{param.name}};')
             else:
                 code('m_${{param.name}} = p->${{param.name}};')
-
-        #
-        # For the l1 cache controller, add the special atomic support which 
-        # includes passing the sequencer a pointer to the controller.
-        #
-        for seq in sequencers:
-            code('''
-m_${{seq}}_ptr->setController(this);
-    ''')
-
-        #
-        # For the DMA controller, pass the sequencer a pointer to the
-        # controller.
-        #
-        if self.ident == "DMA":
-            if not contains_dma_sequencer:
-                self.error("The DMA controller must include the sequencer " \
-                           "configuration parameter")
-
-            code('''
-m_dma_sequencer_ptr->setController(this);
-''')
+            if re.compile("sequencer").search(param.name):
+                code('m_${{param.name}}_ptr->setController(this);')
             
-        code('m_num_controllers++;')
         for var in self.objects:
             if var.ident.find("mandatoryQueue") >= 0:
                 code('''
@@ -545,9 +526,6 @@ $c_ident::init()
     MachineType machine_type = string_to_MachineType("${{var.machine.ident}}");
     int base M5_VAR_USED = MachineType_base_number(machine_type);
 
-    m_machineID.type = MachineType_${ident};
-    m_machineID.num = m_version;
-
     // initialize objects
 
 ''')
@@ -690,19 +668,14 @@ $vid->setDescription("[Version " + to_string(m_version) + ", ${ident}, name=${{v
         code.dedent()
         code('''
     AbstractController::init();
-    clearStats();
+    resetStats();
 }
 ''')
 
-        has_mandatory_q = False
+        mq_ident = "NULL"
         for port in self.in_ports:
             if port.code.find("mandatoryQueue_ptr") >= 0:
-                has_mandatory_q = True
-
-        if has_mandatory_q:
-            mq_ident = "m_%s_mandatoryQueue_ptr" % self.ident
-        else:
-            mq_ident = "NULL"
+                mq_ident = "m_%s_mandatoryQueue_ptr" % self.ident
 
         seq_ident = "NULL"
         for param in self.config_parameters:
@@ -715,12 +688,15 @@ $vid->setDescription("[Version " + to_string(m_version) + ", ${ident}, name=${{v
 void
 $c_ident::regStats()
 {
+    AbstractController::regStats();
+
     if (m_version == 0) {
         for (${ident}_Event event = ${ident}_Event_FIRST;
              event < ${ident}_Event_NUM; ++event) {
             Stats::Vector *t = new Stats::Vector();
             t->init(m_num_controllers);
-            t->name(name() + "." + ${ident}_Event_to_string(event));
+            t->name(g_system_ptr->name() + ".${c_ident}." +
+                ${ident}_Event_to_string(event));
             t->flags(Stats::pdf | Stats::total | Stats::oneline |
                      Stats::nozero);
 
@@ -737,7 +713,8 @@ $c_ident::regStats()
 
                 Stats::Vector *t = new Stats::Vector();
                 t->init(m_num_controllers);
-                t->name(name() + "." + ${ident}_State_to_string(state) +
+                t->name(g_system_ptr->name() + ".${c_ident}." +
+                        ${ident}_State_to_string(state) +
                         "." + ${ident}_Event_to_string(event));
 
                 t->flags(Stats::pdf | Stats::total | Stats::oneline |
@@ -842,7 +819,7 @@ $c_ident::print(ostream& out) const
     out << "[$c_ident " << m_version << "]";
 }
 
-void $c_ident::clearStats()
+void $c_ident::resetStats()
 {
     for (int state = 0; state < ${ident}_State_NUM; state++) {
         for (int event = 0; event < ${ident}_Event_NUM; event++) {
@@ -854,7 +831,7 @@ void $c_ident::clearStats()
         m_event_counters[event] = 0;
     }
 
-    AbstractController::clearStats();
+    AbstractController::resetStats();
 }
 ''')