arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher

[gem5.git] / src / mem / tport.cc

diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 9f9403a22ecdc560dd6ca6f4230ee955ff0827ad..4de495e22f6d376ea65b547437ebc95384d70a0a 100644 (file)
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -41,11 +41,11 @@
  *          Andreas Hansson
  */
 
-#include "mem/mem_object.hh"
 #include "mem/tport.hh"
+#include "sim/sim_object.hh"
 
 SimpleTimingPort::SimpleTimingPort(const std::string& _name,
-                                   MemObject* _owner) :
+                                   SimObject* _owner) :
     QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
 {
 }
@@ -53,7 +53,7 @@ SimpleTimingPort::SimpleTimingPort(const std::string& _name,
 void
 SimpleTimingPort::recvFunctional(PacketPtr pkt)
 {
-    if (!respQueue.checkFunctional(pkt)) {
+    if (!respQueue.trySatisfyFunctional(pkt)) {
         // do an atomic access and throw away the returned latency
         recvAtomic(pkt);
     }
@@ -63,9 +63,11 @@ bool
 SimpleTimingPort::recvTimingReq(PacketPtr pkt)
 {
     // the SimpleTimingPort should not be used anywhere where there is
-    // a need to deal with inhibited packets
-    if (pkt->memInhibitAsserted())
-        panic("SimpleTimingPort should never see an inhibited request\n");
+    // a need to deal with snoop responses and their flow control
+    // requirements
+    if (pkt->cacheResponding())
+        panic("SimpleTimingPort should never see packets with the "
+              "cacheResponding flag set\n");
 
     bool needsResponse = pkt->needsResponse();
     Tick latency = recvAtomic(pkt);