Hook up i915 driver to new DRI2 infrastructure.

[mesa.git] / src / mesa / drivers / dri / i915 / i830_reg.h

diff --git a/src/mesa/drivers/dri/i915/i830_reg.h b/src/mesa/drivers/dri/i915/i830_reg.h
index 69dc333d2c1083be914a6c1d1291bacdfdf2bd0f..41280bca7ce3504caf7c7407c7cf677f6a0094e3 100644 (file)
--- a/src/mesa/drivers/dri/i915/i830_reg.h
+++ b/src/mesa/drivers/dri/i915/i830_reg.h
@@ -205,21 +205,6 @@
 #define ENABLE_DST_ABLEND_FACTOR       (1<<5)
 #define DST_ABLEND_FACT(x)             (x)
 
-#define BLENDFACT_ZERO                 0x01
-#define BLENDFACT_ONE                  0x02
-#define BLENDFACT_SRC_COLR             0x03
-#define BLENDFACT_INV_SRC_COLR                 0x04
-#define BLENDFACT_SRC_ALPHA            0x05
-#define BLENDFACT_INV_SRC_ALPHA        0x06
-#define BLENDFACT_DST_ALPHA            0x07
-#define BLENDFACT_INV_DST_ALPHA        0x08
-#define BLENDFACT_DST_COLR             0x09
-#define BLENDFACT_INV_DST_COLR         0x0a
-#define BLENDFACT_SRC_ALPHA_SATURATE   0x0b
-#define BLENDFACT_CONST_COLOR          0x0c
-#define BLENDFACT_INV_CONST_COLOR      0x0d
-#define BLENDFACT_CONST_ALPHA          0x0e
-#define BLENDFACT_INV_CONST_ALPHA      0x0f
 
 /* _3DSTATE_MAP_BLEND_ARG, p152 */
 #define _3DSTATE_MAP_BLEND_ARG_CMD(stage)      (CMD_3D|(0x0e<<24)|((stage)<<20))
@@ -363,19 +348,6 @@
 #define SRC_BLND_FACT(x)               ((x)<<6)
 #define DST_BLND_FACT(x)               (x)
 
-/* Use the blendfact defines for BLND_FACTOR macros */
-#if 0
-#define BLENDFACT_ZERO                 0x01
-#define BLENDFACT_ONE                  0x02
-#define BLENDFACT_SRC_COLR             0x03
-#define BLENDFACT_INV_SRC_COLR                 0x04
-#define BLENDFACT_SRC_ALPHA            0x05
-#define BLENDFACT_INV_SRC_ALPHA        0x06
-#define BLENDFACT_DST_ALPHA            0x07
-#define BLENDFACT_INV_DST_ALPHA        0x08
-#define BLENDFACT_CONST_ALPHA          0x0e
-#define BLENDFACT_INV_CONST_ALPHA      0x0f
-#endif
 
 /* _3DSTATE_MODES_2, p192 */
 #define _3DSTATE_MODES_2_CMD           (CMD_3D|(0x0f<<24))
@@ -387,14 +359,6 @@
 #define ALPHA_REF_VALUE(x)             (x)
 
 #define ALPHA_TEST_REF_MASK            0x3fff
-#define COMPAREFUNC_ALWAYS             0
-#define COMPAREFUNC_NEVER              0x1
-#define COMPAREFUNC_LESS               0x2
-#define COMPAREFUNC_EQUAL              0x3
-#define COMPAREFUNC_LEQUAL             0x4
-#define COMPAREFUNC_GREATER            0x5
-#define COMPAREFUNC_NOTEQUAL           0x6
-#define COMPAREFUNC_GEQUAL             0x7
 
 /* _3DSTATE_MODES_3, p193 */
 #define _3DSTATE_MODES_3_CMD           (CMD_3D|(0x02<<24))
@@ -443,10 +407,10 @@
 #define LOGICOP_SET                    0xf
 #define MODE4_ENABLE_STENCIL_TEST_MASK ((1<<17)|(0xff00))
 #define ENABLE_STENCIL_TEST_MASK       (1<<17)
-#define STENCIL_TEST_MASK(x)           ((x)<<8)
+#define STENCIL_TEST_MASK(x)           (((x)&0xff)<<8)
 #define MODE4_ENABLE_STENCIL_WRITE_MASK        ((1<<16)|(0x00ff))
 #define ENABLE_STENCIL_WRITE_MASK      (1<<16)
-#define STENCIL_WRITE_MASK(x)          (x)
+#define STENCIL_WRITE_MASK(x)          ((x)&0xff)
 
 /* _3DSTATE_MODES_5, p196 */
 #define _3DSTATE_MODES_5_CMD           (CMD_3D|(0x0c<<24))
@@ -495,15 +459,6 @@
 #define STENCIL_PASS_DEPTH_FAIL_OP(x)  ((x)<<17)
 #define STENCIL_PASS_DEPTH_PASS_OP(x)  ((x)<<14)
 
-#define STENCILOP_KEEP                 0
-#define STENCILOP_ZERO                 0x1
-#define STENCILOP_REPLACE              0x2
-#define STENCILOP_INCRSAT              0x3
-#define STENCILOP_DECRSAT              0x4
-#define STENCILOP_INCR                 0x5
-#define STENCILOP_DECR                 0x6
-#define STENCILOP_INVERT               0x7
-
 #define ENABLE_STENCIL_TEST_FUNC_MASK  ((1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9))
 #define ENABLE_STENCIL_TEST_FUNC       (1<<13)
 /* Uses COMPAREFUNC */
@@ -599,8 +554,8 @@
 #define    MAPSURF_4BIT_INDEXED                   (7<<6)
 #define TM0S1_MT_FORMAT_MASK         (0x7 << 3)
 #define TM0S1_MT_FORMAT_SHIFT        3
-#define    MT_4BIT_IDX_ARGB8888                   (7<<3) /* SURFACE_4BIT_INDEXED */
-#define    MT_8BIT_IDX_RGB565             (0<<3) /* SURFACE_8BIT_INDEXED */
+#define    MT_4BIT_IDX_ARGB8888                   (7<<3)       /* SURFACE_4BIT_INDEXED */
+#define    MT_8BIT_IDX_RGB565             (0<<3)       /* SURFACE_8BIT_INDEXED */
 #define    MT_8BIT_IDX_ARGB1555                   (1<<3)
 #define    MT_8BIT_IDX_ARGB4444                   (2<<3)
 #define    MT_8BIT_IDX_AY88               (3<<3)
@@ -608,9 +563,9 @@
 #define    MT_8BIT_IDX_BUMP_88DVDU        (5<<3)
 #define    MT_8BIT_IDX_BUMP_655LDVDU      (6<<3)
 #define    MT_8BIT_IDX_ARGB8888                   (7<<3)
-#define    MT_8BIT_I8                     (0<<3) /* SURFACE_8BIT */
+#define    MT_8BIT_I8                     (0<<3)       /* SURFACE_8BIT */
 #define    MT_8BIT_L8                     (1<<3)
-#define    MT_16BIT_RGB565                (0<<3) /* SURFACE_16BIT */
+#define    MT_16BIT_RGB565                (0<<3)       /* SURFACE_16BIT */
 #define    MT_16BIT_ARGB1555              (1<<3)
 #define    MT_16BIT_ARGB4444              (2<<3)
 #define    MT_16BIT_AY88                  (3<<3)
@@ -618,16 +573,17 @@
 #define    MT_16BIT_BUMP_88DVDU                   (5<<3)
 #define    MT_16BIT_BUMP_655LDVDU         (6<<3)
 #define    MT_16BIT_DIB_RGB565_8888       (7<<3)
-#define    MT_32BIT_ARGB8888              (0<<3) /* SURFACE_32BIT */
+#define    MT_32BIT_ARGB8888              (0<<3)       /* SURFACE_32BIT */
 #define    MT_32BIT_ABGR8888              (1<<3)
+#define    MT_32BIT_XRGB8888              (2<<3)       /* XXX: Guess from i915_reg.h */
 #define    MT_32BIT_BUMP_XLDVDU_8888      (6<<3)
 #define    MT_32BIT_DIB_8888              (7<<3)
-#define    MT_411_YUV411                  (0<<3) /* SURFACE_411 */
-#define    MT_422_YCRCB_SWAPY             (0<<3) /* SURFACE_422 */
+#define    MT_411_YUV411                  (0<<3)       /* SURFACE_411 */
+#define    MT_422_YCRCB_SWAPY             (0<<3)       /* SURFACE_422 */
 #define    MT_422_YCRCB_NORMAL            (1<<3)
 #define    MT_422_YCRCB_SWAPUV            (2<<3)
 #define    MT_422_YCRCB_SWAPUVY                   (3<<3)
-#define    MT_COMPRESS_DXT1               (0<<3) /* SURFACE_COMPRESSED */
+#define    MT_COMPRESS_DXT1               (0<<3)       /* SURFACE_COMPRESSED */
 #define    MT_COMPRESS_DXT2_3             (1<<3)
 #define    MT_COMPRESS_DXT4_5             (2<<3)
 #define    MT_COMPRESS_FXT1               (3<<3)
@@ -637,6 +593,7 @@
 
 #define TM0S2_PITCH_SHIFT               21
 #define TM0S2_CUBE_FACE_ENA_SHIFT       15
+#define TM0S2_CUBE_FACE_ENA_MASK        (1<<15)
 #define TM0S2_MAP_FORMAT                (1<<14)
 #define TM0S2_VERTICAL_LINE_STRIDE      (1<<13)
 #define TM0S2_VERITCAL_LINE_STRIDE_OFF  (1<<12)