i965: Support CS in update_stage_texture_surfaces
[mesa.git] / src / mesa / drivers / dri / i915 / i830_vtbl.c
index 8b255966904102f926abd558452b234ec1973afb..8ed8ff555ba66ea17b574a7d6572026587dc2516 100644 (file)
@@ -1,6 +1,6 @@
 /**************************************************************************
  * 
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2003 VMware, Inc.
  * All Rights Reserved.
  * 
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -18,7 +18,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -39,6 +39,7 @@
 #include "swrast_setup/swrast_setup.h"
 #include "main/renderbuffer.h"
 #include "main/framebuffer.h"
+#include "main/fbobject.h"
 
 #define FILE_DEBUG_FLAG DEBUG_STATE
 
@@ -133,27 +134,28 @@ i830_render_start(struct intel_context *intel)
             GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
                           ~TEXCOORDTYPE_MASK);
 
-            switch (sz) {
-            case 1:
-            case 2:
-               emit = EMIT_2F;
-               sz = 2;
-               mcs |= TEXCOORDTYPE_CARTESIAN;
-               break;
-            case 3:
+            if (intel->ctx.Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
                emit = EMIT_3F;
                sz = 3;
                mcs |= TEXCOORDTYPE_VECTOR;
-               break;
-            case 4:
-               emit = EMIT_3F_XYW;
-               sz = 3;
-               mcs |= TEXCOORDTYPE_HOMOGENEOUS;
-               break;
-            default:
-               continue;
-            };
-
+            } else {
+               switch (sz) {
+               case 1:
+               case 2:
+               case 3:
+                  emit = EMIT_2F;
+                  sz = 2;
+                  mcs |= TEXCOORDTYPE_CARTESIAN;
+                  break;
+               case 4:
+                  emit = EMIT_3F_XYW;
+                  sz = 3;
+                  mcs |= TEXCOORDTYPE_HOMOGENEOUS;
+                  break;
+               default:
+                  continue;
+               }
+            }
 
             EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
             v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
@@ -178,8 +180,6 @@ i830_render_start(struct intel_context *intel)
        v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
        mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
        index_bitset != i830->last_index_bitset) {
-      int k;
-
       I830_STATECHANGE(i830, I830_UPLOAD_CTX);
 
       /* Must do this *after* statechange, so as not to affect
@@ -198,8 +198,7 @@ i830_render_start(struct intel_context *intel)
       i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
       i830->last_index_bitset = index_bitset;
 
-      k = i830_check_vertex_size(intel, intel->vertex_size);
-      assert(k);
+      assert(i830_check_vertex_size(intel, intel->vertex_size));
    }
 }
 
@@ -368,7 +367,7 @@ i830_emit_invarient_state(struct intel_context *intel)
 
 
 #define emit( intel, state, size )                     \
-   intel_batchbuffer_data(intel, state, size, false)
+   intel_batchbuffer_data(intel, state, size)
 
 static GLuint
 get_dirty(struct i830_hw_state *state)
@@ -433,8 +432,8 @@ i830_emit_state(struct intel_context *intel)
     * batchbuffer fills up.
     */
    intel_batchbuffer_require_space(intel,
-                                  get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
-                                  false);
+                                  get_state_size(state) +
+                                   INTEL_PRIM_EMIT_SIZE);
    count = 0;
  again:
    aper_count = 0;
@@ -512,10 +511,10 @@ i830_emit_state(struct intel_context *intel)
 
       OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
       OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
-      OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
       OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
       OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
       OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
+      OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
 
       assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
       OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
@@ -584,22 +583,22 @@ i830_destroy_context(struct intel_context *intel)
 
 static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 {
-   [MESA_FORMAT_ARGB8888] = DV_PF_8888,
-   [MESA_FORMAT_XRGB8888] = DV_PF_8888,
-   [MESA_FORMAT_RGB565] = DV_PF_565,
-   [MESA_FORMAT_ARGB1555] = DV_PF_1555,
-   [MESA_FORMAT_ARGB4444] = DV_PF_4444,
+   [MESA_FORMAT_B8G8R8A8_UNORM] = DV_PF_8888,
+   [MESA_FORMAT_B8G8R8X8_UNORM] = DV_PF_8888,
+   [MESA_FORMAT_B5G6R5_UNORM] = DV_PF_565,
+   [MESA_FORMAT_B5G5R5A1_UNORM] = DV_PF_1555,
+   [MESA_FORMAT_B4G4R4A4_UNORM] = DV_PF_4444,
 };
 
 static bool
 i830_render_target_supported(struct intel_context *intel,
                             struct gl_renderbuffer *rb)
 {
-   gl_format format = rb->Format;
+   mesa_format format = rb->Format;
 
-   if (format == MESA_FORMAT_S8_Z24 ||
-       format == MESA_FORMAT_X8_Z24 ||
-       format == MESA_FORMAT_Z16) {
+   if (format == MESA_FORMAT_Z24_UNORM_S8_UINT ||
+       format == MESA_FORMAT_Z24_UNORM_X8_UINT ||
+       format == MESA_FORMAT_Z_UNORM16) {
       return true;
    }
 
@@ -692,8 +691,8 @@ i830_set_draw_region(struct intel_context *intel,
    state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
    state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x;
    state->Buffer[I830_DESTREG_DRAWRECT3] =
-      ((ctx->DrawBuffer->Width + draw_x) & 0xffff) |
-      ((ctx->DrawBuffer->Height + draw_y) << 16);
+      ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
+      ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
    state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x;
    state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
 
@@ -731,9 +730,9 @@ i830_update_draw_buffer(struct intel_context *intel)
     */
    if (ctx->NewState & _NEW_BUFFERS) {
       /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
-      _mesa_update_framebuffer(ctx);
+      _mesa_update_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer);
       /* this updates the DrawBuffer's Width/Height if it's a FBO */
-      _mesa_update_draw_buffer_bounds(ctx);
+      _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
    }
 
    if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
@@ -769,7 +768,7 @@ i830_update_draw_buffer(struct intel_context *intel)
       /* Get the intel_renderbuffer for the single colorbuffer we're drawing
        * into.
        */
-      if (fb->Name == 0) {
+      if (_mesa_is_winsys_fbo(fb)) {
         /* drawing to window system buffer */
         if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT)
            colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT);
@@ -806,7 +805,7 @@ i830_update_draw_buffer(struct intel_context *intel)
 
    /* Check for stencil fallback. */
    if (irbStencil && irbStencil->mt) {
-      assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24);
+      assert(intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT);
       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
    } else if (irbStencil && !irbStencil->mt) {
       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
@@ -819,15 +818,14 @@ i830_update_draw_buffer(struct intel_context *intel)
     * we still need to set up the shared depth/stencil state so we can use it.
     */
    if (depthRegion == NULL && irbStencil && irbStencil->mt
-       && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) {
+       && intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT) {
       depthRegion = irbStencil->mt->region;
    }
 
    /*
     * Update depth and stencil test state
     */
-   ctx->Driver.Enable(ctx, GL_DEPTH_TEST,
-                     (ctx->Depth.Test && fb->Visual.depthBits > 0));
+   ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
    ctx->Driver.Enable(ctx, GL_STENCIL_TEST,
                      (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0));
 
@@ -835,15 +833,10 @@ i830_update_draw_buffer(struct intel_context *intel)
                                fb->_NumColorDrawBuffers);
    intel->NewGLState |= _NEW_BUFFERS;
 
-   /* update viewport since it depends on window size */
-   intelCalcViewport(ctx);
-
    /* Set state we know depends on drawable parameters:
     */
-   ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
-                      ctx->Scissor.Width, ctx->Scissor.Height);
-
-   ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far);
+   intelCalcViewport(ctx);
+   ctx->Driver.Scissor(ctx);
 
    /* Update culling direction which changes depending on the
     * orientation of the buffer:
@@ -881,12 +874,6 @@ i830_invalidate_state(struct intel_context *intel, GLuint new_state)
       i830_update_provoking_vertex(&intel->ctx);
 }
 
-static bool
-i830_is_hiz_depth_format(struct intel_context *intel, gl_format format)
-{
-   return false;
-}
-
 void
 i830InitVtbl(struct i830_context *i830)
 {
@@ -904,5 +891,4 @@ i830InitVtbl(struct i830_context *i830)
    i830->intel.vtbl.finish_batch = intel_finish_vb;
    i830->intel.vtbl.invalidate_state = i830_invalidate_state;
    i830->intel.vtbl.render_target_supported = i830_render_target_supported;
-   i830->intel.vtbl.is_hiz_depth_format = i830_is_hiz_depth_format;
 }