fix up radeon span functions using latest r200 code from Brian,

[mesa.git] / src / mesa / drivers / dri / i915 / i915_metaops.c

diff --git a/src/mesa/drivers/dri/i915/i915_metaops.c b/src/mesa/drivers/dri/i915/i915_metaops.c
index 809419bd77554cc03479af411d912be0d7d2a1fa..a3d22b7bd07eb80a60fb40073111a6572307fce2 100644 (file)
--- a/src/mesa/drivers/dri/i915/i915_metaops.c
+++ b/src/mesa/drivers/dri/i915/i915_metaops.c
@@ -240,7 +240,7 @@ static void set_no_texture( i915ContextPtr i915 )
    i915->meta.emitted &= ~I915_UPLOAD_PROGRAM;
 }
 
-
+#if 0
 static void enable_texture_blend_replace( i915ContextPtr i915 )
 {
    static const GLuint prog[] = {
@@ -323,7 +323,7 @@ static void set_tex_rect_source( i915ContextPtr i915,
 
    i915->meta.emitted &= ~I915_UPLOAD_TEX(0);
 }
-
+#endif
 
 /* Select between front and back draw buffers.
  */
@@ -334,6 +334,7 @@ static void set_draw_offset( i915ContextPtr i915,
    i915->meta.emitted &= ~I915_UPLOAD_BUFFERS;
 }
 
+#if 0
 /* Setup an arbitary draw format, useful for targeting texture or agp
  * memory.
  */
@@ -352,6 +353,7 @@ static void set_draw_format( i915ContextPtr i915,
 /*    fprintf(stderr, "%s: DV1: %x\n",  */
 /*        __FUNCTION__, i915->meta.Buffer[I915_DESTREG_DV1]); */
 }
+#endif
 
 static void set_vertex_format( i915ContextPtr i915 )
 {
@@ -473,10 +475,10 @@ i915ClearWithTris(intelContextPtr intel, GLbitfield mask,
     * The active cliprects will be applied as for any other geometry.
     */
 
-   if (mask & DD_FRONT_LEFT_BIT) { 
+   if (mask & BUFFER_BIT_FRONT_LEFT) { 
       set_no_depth_stencil_write( i915 );
       set_color_mask( i915, GL_TRUE );
-      set_draw_offset( i915, screen->frontOffset );
+      set_draw_offset( i915, screen->front.offset );
 
       draw_quad(i915, x0, x1, y0, y1,
                intel->clear_red, intel->clear_green, 
@@ -484,10 +486,10 @@ i915ClearWithTris(intelContextPtr intel, GLbitfield mask,
                0, 0, 0, 0);
    }
 
-   if(mask & DD_BACK_LEFT_BIT) {
+   if (mask & BUFFER_BIT_BACK_LEFT) {
       set_no_depth_stencil_write( i915 );
       set_color_mask( i915, GL_TRUE );
-      set_draw_offset( i915, screen->backOffset );
+      set_draw_offset( i915, screen->back.offset );
 
       draw_quad(i915, x0, x1, y0, y1,
                intel->clear_red, intel->clear_green,
@@ -495,13 +497,13 @@ i915ClearWithTris(intelContextPtr intel, GLbitfield mask,
                0, 0, 0, 0);
    }
 
-   if(mask & DD_STENCIL_BIT) {
+   if (mask & BUFFER_BIT_STENCIL) {
       set_stencil_replace( i915, 
                           intel->ctx.Stencil.WriteMask[0], 
                           intel->ctx.Stencil.Clear);
       
       set_color_mask( i915, GL_FALSE );
-      set_draw_offset( i915, screen->frontOffset ); /* could be either? */
+      set_draw_offset( i915, screen->front.offset ); /* could be either? */
 
       draw_quad( i915, x0, x1, y0, y1, 0, 0, 0, 0, 0, 0, 0, 0 );
    }