i965: Re-enable fast color clears for GEN11.

[mesa.git] / src / mesa / drivers / dri / i915 / i915_reg.h

diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h
index 8891e11c6fd22ee0101712eef7d082443f78ccbc..e09f1f1f9c83478a1cf949ef3044acb062d7dab0 100644 (file)
--- a/src/mesa/drivers/dri/i915/i915_reg.h
+++ b/src/mesa/drivers/dri/i915/i915_reg.h
@@ -1,6 +1,6 @@
 /**************************************************************************
  * 
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2003 VMware, Inc.
  * All Rights Reserved.
  * 
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -18,7 +18,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -86,27 +86,15 @@
 #define BFM_ENABLE_STENCIL_WRITE_MASK     (1<<16)
 #define BFM_STENCIL_TEST_MASK_SHIFT       8
 #define BFM_STENCIL_TEST_MASK_MASK        (0xff<<8)
+#define BFM_STENCIL_TEST_MASK(x)         (((x)&0xff) << 8)
 #define BFM_STENCIL_WRITE_MASK_SHIFT      0
 #define BFM_STENCIL_WRITE_MASK_MASK       (0xff<<0)
+#define BFM_STENCIL_WRITE_MASK(x)        ((x)&0xff)
 
 
 
 /* 3DSTATE_BIN_CONTROL p141 */
 
-/* p143 */
-#define _3DSTATE_BUF_INFO_CMD  (CMD_3D | (0x1d<<24) | (0x8e<<16) | 1)
-/* Dword 1 */
-#define BUF_3D_ID_COLOR_BACK   (0x3<<24)
-#define BUF_3D_ID_DEPTH        (0x7<<24)
-#define BUF_3D_USE_FENCE       (1<<23)
-#define BUF_3D_TILED_SURFACE   (1<<22)
-#define BUF_3D_TILE_WALK_X     0
-#define BUF_3D_TILE_WALK_Y     (1<<21)
-#define BUF_3D_PITCH(x)         (((x)/4)<<2)
-/* Dword 2 */
-#define BUF_3D_ADDR(x)         ((x) & ~0x3)
-
-
 /* 3DSTATE_CHROMA_KEY */
 
 /* 3DSTATE_CLEAR_PARAMETERS, p150 */
@@ -155,6 +143,7 @@
 /* p161 */
 #define _3DSTATE_DST_BUF_VARS_CMD      (CMD_3D | (0x1d<<24) | (0x85<<16))
 /* Dword 1 */
+#define CLASSIC_EARLY_DEPTH            (1<<31)
 #define TEX_DEFAULT_COLOR_OGL           (0<<30)
 #define TEX_DEFAULT_COLOR_D3D           (1<<30)
 #define ZR_EARLY_DEPTH                  (1<<29)
@@ -308,7 +297,9 @@
 #define TEXKILL_4D                      (1<<9)
 #define ENABLE_LINE_STRIP_PROVOKE_VRTX (1<<8)
 #define ENABLE_TRI_FAN_PROVOKE_VRTX    (1<<5)
+#define LINE_STRIP_PROVOKE_VRTX_MASK   (3 << 6)
 #define LINE_STRIP_PROVOKE_VRTX(x)     ((x)<<6)
+#define TRI_FAN_PROVOKE_VRTX_MASK      (3 << 3)
 #define TRI_FAN_PROVOKE_VRTX(x)        ((x)<<3)
 
 /* _3DSTATE_SCISSOR_ENABLE, p256 */
@@ -370,13 +361,6 @@
 /* p222 */
 
 
-#define I915_MAX_TEX_INDIRECT 4
-#define I915_MAX_TEX_INSN     32
-#define I915_MAX_ALU_INSN     64
-#define I915_MAX_DECL_INSN    27
-#define I915_MAX_TEMPORARY    16
-
-
 /* Each instruction is 3 dwords long, though most don't require all
  * this space.  Maximum of 123 instructions.  Smaller maxes per insn
  * type.
@@ -635,9 +619,9 @@
 #define    MT_32BIT_AWVU2101010                   (0xA<<3)
 #define    MT_32BIT_GR1616                (0xB<<3)
 #define    MT_32BIT_VU1616                (0xC<<3)
-#define    MT_32BIT_xI824                 (0xD<<3)
-#define    MT_32BIT_xA824                 (0xE<<3)
-#define    MT_32BIT_xL824                 (0xF<<3)
+#define    MT_32BIT_x8I24                 (0xD<<3)
+#define    MT_32BIT_x8L24                 (0xE<<3)
+#define    MT_32BIT_x8A24                 (0xF<<3)
 #define    MT_422_YCRCB_SWAPY             (0<<3)       /* SURFACE_422 */
 #define    MT_422_YCRCB_NORMAL            (1<<3)
 #define    MT_422_YCRCB_SWAPUV            (2<<3)