-static void i915StencilFunc(GLcontext *ctx, GLenum func, GLint ref,
- GLuint mask)
+static void
+i915StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func, GLint ref,
+ GLuint mask)
{
i915ContextPtr i915 = I915_CONTEXT(ctx);
int test = intel_translate_compare_func( func );
(test << S5_STENCIL_TEST_FUNC_SHIFT));
}
-static void i915StencilMask(GLcontext *ctx, GLuint mask)
+static void
+i915StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask)
{
i915ContextPtr i915 = I915_CONTEXT(ctx);
}
-static void i915StencilOp(GLcontext *ctx, GLenum fail, GLenum zfail,
- GLenum zpass)
+static void
+i915StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail, GLenum zfail,
+ GLenum zpass)
{
i915ContextPtr i915 = I915_CONTEXT(ctx);
int fop = intel_translate_stencil_op(fail);
I915_STATECHANGE(i915, I915_UPLOAD_CTX);
- if (ctx->Color._LogicOpEnabled) {
+ if (RGBA_LOGICOP_ENABLED(ctx)) {
i915->state.Ctx[I915_CTXREG_LIS5] |= S5_LOGICOP_ENABLE;
i915->state.Ctx[I915_CTXREG_LIS6] &= ~S6_CBUF_BLEND_ENABLE;
} else {
GLboolean enabled;
GLboolean try_pixel_fog;
- if (ctx->FragmentProgram._Active) {
+ if (ctx->FragmentProgram._Enabled) {
/* Pull in static fog state from program */
mode = ctx->FragmentProgram._Current->FogOption;
i915->state.Ctx[I915_CTXREG_LIS5] &= ~S5_FOG_ENABLE;
}
- if (enabled) {
- _tnl_allow_vertex_fog( ctx, (i915->vertex_fog == I915_FOG_VERTEX) );
- _tnl_allow_pixel_fog( ctx, (i915->vertex_fog != I915_FOG_VERTEX) );
- }
+ /* always enbale pixel fog
+ * vertex fog use precaculted fog coord will conflict with appended
+ * fog program
+ */
+ _tnl_allow_vertex_fog( ctx, 0 );
+ _tnl_allow_pixel_fog( ctx, 1 );
}
static void i915Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *param)
}
break;
+ case GL_POLYGON_SMOOTH:
+ FALLBACK( &i915->intel, I915_FALLBACK_POLYGON_SMOOTH, state );
+ break;
+
+ case GL_POINT_SMOOTH:
+ FALLBACK( &i915->intel, I915_FALLBACK_POINT_SMOOTH, state );
+ break;
+
default:
;
}
I1_LOAD_S(4) |
I1_LOAD_S(5) |
I1_LOAD_S(6) |
- (4));
+ (3));
i915->state.Ctx[I915_CTXREG_LIS2] = 0;
i915->state.Ctx[I915_CTXREG_LIS4] = 0;
i915->state.Ctx[I915_CTXREG_LIS5] = 0;
{
I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
+ /* color buffer offset/stride */
i915->state.Buffer[I915_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
i915->state.Buffer[I915_DESTREG_CBUFADDR1] =
(BUF_3D_ID_COLOR_BACK |
- BUF_3D_PITCH(screen->front.pitch * screen->cpp) |
+ BUF_3D_PITCH(screen->front.pitch) | /* pitch in bytes */
BUF_3D_USE_FENCE);
+ /*i915->state.Buffer[I915_DESTREG_CBUFADDR2] is the offset */
+ /* depth/Z buffer offset/stride */
i915->state.Buffer[I915_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
i915->state.Buffer[I915_DESTREG_DBUFADDR1] =
(BUF_3D_ID_DEPTH |
- BUF_3D_PITCH(screen->depth.pitch * screen->cpp) |
+ BUF_3D_PITCH(screen->depth.pitch) | /* pitch in bytes */
BUF_3D_USE_FENCE);
i915->state.Buffer[I915_DESTREG_DBUFADDR2] = screen->depth.offset;
i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
+ /* color/depth pixel format */
switch (screen->fbFormat) {
case DV_PF_555:
case DV_PF_565:
DEPTH_FRMT_24_FIXED_8_OTHER);
break;
}
+
+ /* scissor */
i915->state.Buffer[I915_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
DISABLE_SCISSOR_RECT);
i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
* we get hardware contexts working.
*/
i915->state.active = (I915_UPLOAD_PROGRAM |
- I915_UPLOAD_STIPPLE |
- I915_UPLOAD_CTX |
- I915_UPLOAD_BUFFERS);
+ I915_UPLOAD_STIPPLE |
+ I915_UPLOAD_CTX |
+ I915_UPLOAD_BUFFERS |
+ I915_UPLOAD_INVARIENT);
}
void i915InitStateFunctions( struct dd_function_table *functions )
functions->PolygonStipple = i915PolygonStipple;
functions->Scissor = i915Scissor;
functions->ShadeModel = i915ShadeModel;
- functions->StencilFunc = i915StencilFunc;
- functions->StencilMask = i915StencilMask;
- functions->StencilOp = i915StencilOp;
+ functions->StencilFuncSeparate = i915StencilFuncSeparate;
+ functions->StencilMaskSeparate = i915StencilMaskSeparate;
+ functions->StencilOpSeparate = i915StencilOpSeparate;
}