#include "swrast_setup/swrast_setup.h"
#include "intel_batchbuffer.h"
+#include "intel_mipmap_tree.h"
#include "intel_regions.h"
#include "intel_tris.h"
#include "intel_fbo.h"
/* Pull apart the vertex format registers and figure out how large a
* vertex is supposed to be.
*/
-static GLboolean
+static bool
i915_check_vertex_size(struct intel_context *intel, GLuint expected)
{
struct i915_context *i915 = i915_context(&intel->ctx);
break;
default:
fprintf(stderr, "bad texcoord fmt %d\n", i);
- return GL_FALSE;
+ return false;
}
lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
}
#define emit(intel, state, size ) \
- intel_batchbuffer_data(intel, state, size, false)
+ intel_batchbuffer_data(intel, state, size)
static GLuint
get_dirty(struct i915_hw_state *state)
* batchbuffer fills up.
*/
intel_batchbuffer_require_space(intel,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
- false);
+ get_state_size(state) +
+ INTEL_PRIM_EMIT_SIZE);
count = 0;
again:
if (intel->batch.bo == NULL) {
aper_array[aper_count++] = intel->batch.bo;
if (dirty & I915_UPLOAD_BUFFERS) {
- aper_array[aper_count++] = state->draw_region->buffer;
+ if (state->draw_region)
+ aper_array[aper_count++] = state->draw_region->bo;
if (state->depth_region)
- aper_array[aper_count++] = state->depth_region->buffer;
+ aper_array[aper_count++] = state->depth_region->bo;
}
if (dirty & I915_UPLOAD_TEX_ALL) {
if (INTEL_DEBUG & DEBUG_STATE)
fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
- count = 14;
+ count = 17;
if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
count++;
- if (state->depth_region)
- count += 3;
BEGIN_BATCH(count);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
- OUT_RELOC(state->draw_region->buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ if (state->draw_region) {
+ OUT_RELOC(state->draw_region->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ } else {
+ OUT_BATCH(0);
+ }
+ OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
+ OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
if (state->depth_region) {
- OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
- OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
- OUT_RELOC(state->depth_region->buffer,
+ OUT_RELOC(state->depth_region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ } else {
+ OUT_BATCH(0);
}
OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
state[1] = buffer_id;
if (region != NULL) {
- state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
+ state[1] |= BUF_3D_PITCH(region->pitch);
if (region->tiling != I915_TILING_NONE) {
state[1] |= BUF_3D_TILED_SURFACE;
if (region->tiling == I915_TILING_Y)
state[1] |= BUF_3D_TILE_WALK_Y;
}
+ } else {
+ /* Fill in a default pitch, since 0 is invalid. We'll be
+ * setting the buffer offset to 0 and not referencing the
+ * buffer, so the pitch could really be any valid value.
+ */
+ state[1] |= BUF_3D_PITCH(4096);
}
}
};
static bool
-i915_render_target_supported(gl_format format)
+i915_render_target_supported(struct intel_context *intel,
+ struct gl_renderbuffer *rb)
{
+ gl_format format = rb->Format;
+
if (format == MESA_FORMAT_S8_Z24 ||
format == MESA_FORMAT_X8_Z24 ||
format == MESA_FORMAT_Z16) {
DSTORG_VERT_BIAS(0x8) | /* .5 */
LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
if (irb != NULL) {
- value |= i915_render_target_format_for_mesa_format[irb->Base.Format];
+ value |= i915_render_target_format_for_mesa_format[intel_rb_format(irb)];
+ } else {
+ value |= DV_PF_8888;
}
/* This isn't quite safe, thus being hidden behind an option. When changing
draw_offset = (draw_y << 16) | draw_x;
+ FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
+ (ctx->DrawBuffer->Width + draw_x > 2048) ||
+ (ctx->DrawBuffer->Height + draw_y > 2048));
/* When changing drawing rectangle offset, an MI_FLUSH is first required. */
if (draw_offset != i915->last_draw_offset) {
- FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
- (ctx->DrawBuffer->Width + draw_x > 2048) ||
- (ctx->DrawBuffer->Height + draw_y > 2048));
-
state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
i915->last_draw_offset = draw_offset;
} else
I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
}
+static void
+i915_update_color_write_enable(struct i915_context *i915, bool enable)
+{
+ uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
+ if (enable)
+ dw |= S6_COLOR_WRITE_ENABLE;
+ else
+ dw &= ~S6_COLOR_WRITE_ENABLE;
+ if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
+ I915_STATECHANGE(i915, I915_UPLOAD_CTX);
+ i915->state.Ctx[I915_CTXREG_LIS6] = dw;
+ }
+}
+
/**
* Update the hardware state for drawing into a window or framebuffer object.
*
static void
i915_update_draw_buffer(struct intel_context *intel)
{
+ struct i915_context *i915 = (struct i915_context *)intel;
struct gl_context *ctx = &intel->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
- struct intel_region *colorRegions[MAX_DRAW_BUFFERS], *depthRegion = NULL;
+ struct intel_region *colorRegion = NULL, *depthRegion = NULL;
struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
- bool fb_has_hiz = intel_framebuffer_has_hiz(fb);
if (!fb) {
/* this can happen during the initial context initialization */
return;
}
- /*
- * If intel_context is using separate stencil, but the depth attachment
- * (gl_framebuffer.Attachment[BUFFER_DEPTH]) has a packed depth/stencil
- * format, then we must install the real depth buffer at fb->_DepthBuffer
- * and set fb->_DepthBuffer->Wrapped before calling _mesa_update_framebuffer.
- * Otherwise, _mesa_update_framebuffer will create and install a swras
- * depth wrapper instead.
- *
- * Ditto for stencil.
- */
irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
- if (irbDepth && irbDepth->Base.Format == MESA_FORMAT_X8_Z24) {
- _mesa_reference_renderbuffer(&fb->_DepthBuffer, &irbDepth->Base);
- irbDepth->Base.Wrapped = fb->Attachment[BUFFER_DEPTH].Renderbuffer;
- }
-
irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
- if (irbStencil && irbStencil->Base.Format == MESA_FORMAT_S8) {
- _mesa_reference_renderbuffer(&fb->_StencilBuffer, &irbStencil->Base);
- irbStencil->Base.Wrapped = fb->Attachment[BUFFER_STENCIL].Renderbuffer;
- }
/* Do this here, not core Mesa, since this function is called from
* many places within the driver.
/* How many color buffers are we drawing into?
*
- * If there are zero buffers or the buffer is too big, don't configure any
- * regions for hardware drawing. We'll fallback to software below. Not
- * having regions set makes some of the software fallback paths faster.
+ * If there is more than one drawbuffer (GL_FRONT_AND_BACK), or the
+ * drawbuffers are too big, we have to fallback to software.
*/
if ((fb->Width > ctx->Const.MaxRenderbufferSize)
- || (fb->Height > ctx->Const.MaxRenderbufferSize)
- || (fb->_NumColorDrawBuffers == 0)) {
- /* writing to 0 */
- colorRegions[0] = NULL;
- }
- else if (fb->_NumColorDrawBuffers > 1) {
- int i;
- struct intel_renderbuffer *irb;
-
- for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
- irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]);
- colorRegions[i] = irb ? irb->region : NULL;
- }
- }
- else {
- /* Get the intel_renderbuffer for the single colorbuffer we're drawing
- * into.
- */
- if (fb->Name == 0) {
- /* drawing to window system buffer */
- if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT)
- colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT);
- else
- colorRegions[0] = intel_get_rb_region(fb, BUFFER_BACK_LEFT);
- }
- else {
- /* drawing to user-created FBO */
- struct intel_renderbuffer *irb;
- irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
- colorRegions[0] = (irb && irb->region) ? irb->region : NULL;
- }
- }
-
- if (!colorRegions[0]) {
- FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, GL_TRUE);
- }
- else {
- FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, GL_FALSE);
+ || (fb->Height > ctx->Const.MaxRenderbufferSize)) {
+ FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
+ } else if (fb->_NumColorDrawBuffers > 1) {
+ FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
+ } else {
+ struct intel_renderbuffer *irb;
+ irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
+ colorRegion = (irb && irb->mt) ? irb->mt->region : NULL;
+ FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
}
/* Check for depth fallback. */
- if (irbDepth && irbDepth->region) {
- assert(!fb_has_hiz || irbDepth->Base.Format != MESA_FORMAT_S8_Z24);
- FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
- depthRegion = irbDepth->region;
- } else if (irbDepth && !irbDepth->region) {
- FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_TRUE);
+ if (irbDepth && irbDepth->mt) {
+ FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
+ depthRegion = irbDepth->mt->region;
+ } else if (irbDepth && !irbDepth->mt) {
+ FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true);
depthRegion = NULL;
} else { /* !irbDepth */
/* No fallback is needed because there is no depth buffer. */
- FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
+ FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
depthRegion = NULL;
}
/* Check for stencil fallback. */
- if (irbStencil && irbStencil->region) {
- if (!intel->has_separate_stencil)
- assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
- if (fb_has_hiz || intel->must_use_separate_stencil)
- assert(irbStencil->Base.Format == MESA_FORMAT_S8);
- if (irbStencil->Base.Format == MESA_FORMAT_S8)
- assert(intel->has_separate_stencil);
- FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
- } else if (irbStencil && !irbStencil->region) {
- FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_TRUE);
+ if (irbStencil && irbStencil->mt) {
+ assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24);
+ FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
+ } else if (irbStencil && !irbStencil->mt) {
+ FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
} else { /* !irbStencil */
/* No fallback is needed because there is no stencil buffer. */
- FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
+ FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
}
/* If we have a (packed) stencil buffer attached but no depth buffer,
* we still need to set up the shared depth/stencil state so we can use it.
*/
- if (depthRegion == NULL && irbStencil && irbStencil->region
- && irbStencil->Base.Format == MESA_FORMAT_S8_Z24) {
- depthRegion = irbStencil->region;
+ if (depthRegion == NULL && irbStencil && irbStencil->mt
+ && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) {
+ depthRegion = irbStencil->mt->region;
}
/*
* Update depth and stencil test state
*/
- if (ctx->Driver.Enable) {
- ctx->Driver.Enable(ctx, GL_DEPTH_TEST,
- (ctx->Depth.Test && fb->Visual.depthBits > 0));
- ctx->Driver.Enable(ctx, GL_STENCIL_TEST,
- (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0));
- }
- else {
- /* Mesa's Stencil._Enabled field is updated when
- * _NEW_BUFFERS | _NEW_STENCIL, but i965 code assumes that the value
- * only changes with _NEW_STENCIL (which seems sensible). So flag it
- * here since this is the _NEW_BUFFERS path.
- */
- intel->NewGLState |= (_NEW_DEPTH | _NEW_STENCIL);
- }
+ ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
+ ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
- intel->vtbl.set_draw_region(intel, colorRegions, depthRegion,
+ i915_update_color_write_enable(i915, colorRegion != NULL);
+
+ intel->vtbl.set_draw_region(intel, &colorRegion, depthRegion,
fb->_NumColorDrawBuffers);
intel->NewGLState |= _NEW_BUFFERS;
/* update viewport since it depends on window size */
-#ifdef I915
intelCalcViewport(ctx);
-#else
- intel->NewGLState |= _NEW_VIEWPORT;
-#endif
+
/* Set state we know depends on drawable parameters:
*/
- if (ctx->Driver.Scissor)
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
- intel->NewGLState |= _NEW_SCISSOR;
-
- if (ctx->Driver.DepthRange)
- ctx->Driver.DepthRange(ctx,
- ctx->Viewport.Near,
- ctx->Viewport.Far);
+ ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
+ ctx->Scissor.Width, ctx->Scissor.Height);
+ ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far);
/* Update culling direction which changes depending on the
* orientation of the buffer:
*/
- if (ctx->Driver.FrontFace)
- ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
- else
- intel->NewGLState |= _NEW_POLYGON;
+ ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
}
static void
(void) dirty;
}
-/** Return false; i915 does not support HiZ. */
-static bool
-i915_is_hiz_depth_format(struct intel_context *intel,
- gl_format format)
-{
- return false;
-}
-
static void
i915_invalidate_state(struct intel_context *intel, GLuint new_state)
{
i915->intel.vtbl.finish_batch = intel_finish_vb;
i915->intel.vtbl.invalidate_state = i915_invalidate_state;
i915->intel.vtbl.render_target_supported = i915_render_target_supported;
- i915->intel.vtbl.is_hiz_depth_format = i915_is_hiz_depth_format;
}
projects / mesa.git / blobdiff