i915: Drop 965+ GL version setup.

[mesa.git] / src / mesa / drivers / dri / i915 / i915_vtbl.c

diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index e09c7878d0f1f4f3ab4a5ed5c4f7b3c73882a23d..3368fe43f2e1ccffaec7cfb571143c5c6457993a 100644 (file)
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -41,6 +41,7 @@
 #include "swrast_setup/swrast_setup.h"
 
 #include "intel_batchbuffer.h"
+#include "intel_mipmap_tree.h"
 #include "intel_regions.h"
 #include "intel_tris.h"
 #include "intel_fbo.h"
@@ -98,7 +99,7 @@ i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
 /* Pull apart the vertex format registers and figure out how large a
  * vertex is supposed to be. 
  */
-static GLboolean
+static bool
 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
 {
    struct i915_context *i915 = i915_context(&intel->ctx);
@@ -159,7 +160,7 @@ i915_check_vertex_size(struct intel_context *intel, GLuint expected)
          break;
       default:
          fprintf(stderr, "bad texcoord fmt %d\n", i);
-         return GL_FALSE;
+         return false;
       }
       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
    }
@@ -222,7 +223,7 @@ i915_emit_invarient_state(struct intel_context *intel)
 
 
 #define emit(intel, state, size )                   \
-   intel_batchbuffer_data(intel, state, size, false)
+   intel_batchbuffer_data(intel, state, size)
 
 static GLuint
 get_dirty(struct i915_hw_state *state)
@@ -305,8 +306,8 @@ i915_emit_state(struct intel_context *intel)
     * batchbuffer fills up.
     */
    intel_batchbuffer_require_space(intel,
-                                  get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
-                                  false);
+                                  get_state_size(state) +
+                                   INTEL_PRIM_EMIT_SIZE);
    count = 0;
  again:
    if (intel->batch.bo == NULL) {
@@ -530,7 +531,7 @@ i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
    state[1] = buffer_id;
 
    if (region != NULL) {
-      state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
+      state[1] |= BUF_3D_PITCH(region->pitch);
 
       if (region->tiling != I915_TILING_NONE) {
         state[1] |= BUF_3D_TILED_SURFACE;
@@ -556,8 +557,11 @@ static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 };
 
 static bool
-i915_render_target_supported(gl_format format)
+i915_render_target_supported(struct intel_context *intel,
+                            struct gl_renderbuffer *rb)
 {
+   gl_format format = rb->Format;
+
    if (format == MESA_FORMAT_S8_Z24 ||
        format == MESA_FORMAT_X8_Z24 ||
        format == MESA_FORMAT_Z16) {
@@ -606,7 +610,7 @@ i915_set_draw_region(struct intel_context *intel,
             DSTORG_VERT_BIAS(0x8) |     /* .5 */
             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
    if (irb != NULL) {
-      value |= i915_render_target_format_for_mesa_format[irb->Base.Format];
+      value |= i915_render_target_format_for_mesa_format[intel_rb_format(irb)];
    } else {
       value |= DV_PF_8888;
    }
@@ -661,12 +665,11 @@ i915_set_draw_region(struct intel_context *intel,
 
    draw_offset = (draw_y << 16) | draw_x;
 
+   FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
+            (ctx->DrawBuffer->Width + draw_x > 2048) ||
+            (ctx->DrawBuffer->Height + draw_y > 2048));
    /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
    if (draw_offset != i915->last_draw_offset) {
-      FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
-               (ctx->DrawBuffer->Width + draw_x > 2048) ||
-               (ctx->DrawBuffer->Height + draw_y > 2048));
-
       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
       i915->last_draw_offset = draw_offset;
    } else
@@ -755,40 +758,40 @@ i915_update_draw_buffer(struct intel_context *intel)
    } else {
       struct intel_renderbuffer *irb;
       irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
-      colorRegion = irb ? irb->region : NULL;
+      colorRegion = (irb && irb->mt) ? irb->mt->region : NULL;
       FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
    }
 
    /* Check for depth fallback. */
-   if (irbDepth && irbDepth->region) {
-      FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
-      depthRegion = irbDepth->region;
-   } else if (irbDepth && !irbDepth->region) {
-      FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_TRUE);
+   if (irbDepth && irbDepth->mt) {
+      FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
+      depthRegion = irbDepth->mt->region;
+   } else if (irbDepth && !irbDepth->mt) {
+      FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true);
       depthRegion = NULL;
    } else { /* !irbDepth */
       /* No fallback is needed because there is no depth buffer. */
-      FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
+      FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
       depthRegion = NULL;
    }
 
    /* Check for stencil fallback. */
-   if (irbStencil && irbStencil->region) {
-      assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
-      FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
-   } else if (irbStencil && !irbStencil->region) {
-      FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_TRUE);
+   if (irbStencil && irbStencil->mt) {
+      assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24);
+      FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
+   } else if (irbStencil && !irbStencil->mt) {
+      FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
    } else { /* !irbStencil */
       /* No fallback is needed because there is no stencil buffer. */
-      FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
+      FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
    }
 
    /* If we have a (packed) stencil buffer attached but no depth buffer,
     * we still need to set up the shared depth/stencil state so we can use it.
     */
-   if (depthRegion == NULL && irbStencil && irbStencil->region
-       && irbStencil->Base.Format == MESA_FORMAT_S8_Z24) {
-      depthRegion = irbStencil->region;
+   if (depthRegion == NULL && irbStencil && irbStencil->mt
+       && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) {
+      depthRegion = irbStencil->mt->region;
    }
 
    /*
@@ -844,14 +847,6 @@ i915_assert_not_dirty( struct intel_context *intel )
    (void) dirty;
 }
 
-/** Return false; i915 does not support HiZ. */
-static bool
-i915_is_hiz_depth_format(struct intel_context *intel,
-                         gl_format format)
-{
-   return false;
-}
-
 static void
 i915_invalidate_state(struct intel_context *intel, GLuint new_state)
 {
@@ -879,5 +874,4 @@ i915InitVtbl(struct i915_context *i915)
    i915->intel.vtbl.finish_batch = intel_finish_vb;
    i915->intel.vtbl.invalidate_state = i915_invalidate_state;
    i915->intel.vtbl.render_target_supported = i915_render_target_supported;
-   i915->intel.vtbl.is_hiz_depth_format = i915_is_hiz_depth_format;
 }