mesa: Change many Type A MESA_FORMATs to meet naming standard

[mesa.git] / src / mesa / drivers / dri / i915 / i915_vtbl.c

diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 62bfa0abf49687d7e7f3671a9409043d0e2dd5c0..e263da0d79aa4b6c0c1f4e68390f36ebdc8f86c7 100644 (file)
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -1,6 +1,6 @@
 /**************************************************************************
  * 
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2003 VMware, Inc.
  * All Rights Reserved.
  * 
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -18,7 +18,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -223,7 +223,7 @@ i915_emit_invarient_state(struct intel_context *intel)
 
 
 #define emit(intel, state, size )                   \
-   intel_batchbuffer_data(intel, state, size, false)
+   intel_batchbuffer_data(intel, state, size)
 
 static GLuint
 get_dirty(struct i915_hw_state *state)
@@ -306,8 +306,8 @@ i915_emit_state(struct intel_context *intel)
     * batchbuffer fills up.
     */
    intel_batchbuffer_require_space(intel,
-                                  get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
-                                  false);
+                                  get_state_size(state) +
+                                   INTEL_PRIM_EMIT_SIZE);
    count = 0;
  again:
    if (intel->batch.bo == NULL) {
@@ -531,7 +531,7 @@ i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
    state[1] = buffer_id;
 
    if (region != NULL) {
-      state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
+      state[1] |= BUF_3D_PITCH(region->pitch);
 
       if (region->tiling != I915_TILING_NONE) {
         state[1] |= BUF_3D_TILED_SURFACE;
@@ -549,19 +549,22 @@ i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 
 static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 {
-   [MESA_FORMAT_ARGB8888] = DV_PF_8888,
-   [MESA_FORMAT_XRGB8888] = DV_PF_8888,
+   [MESA_FORMAT_B8G8R8A8_UNORM] = DV_PF_8888,
+   [MESA_FORMAT_B8G8R8X8_UNORM] = DV_PF_8888,
    [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS,
    [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS,
    [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS,
 };
 
 static bool
-i915_render_target_supported(struct intel_context *intel, gl_format format)
+i915_render_target_supported(struct intel_context *intel,
+                            struct gl_renderbuffer *rb)
 {
+   mesa_format format = rb->Format;
+
    if (format == MESA_FORMAT_S8_Z24 ||
        format == MESA_FORMAT_X8_Z24 ||
-       format == MESA_FORMAT_Z16) {
+       format == MESA_FORMAT_Z_UNORM16) {
       return true;
    }
 
@@ -662,12 +665,11 @@ i915_set_draw_region(struct intel_context *intel,
 
    draw_offset = (draw_y << 16) | draw_x;
 
+   FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
+            (ctx->DrawBuffer->Width + draw_x > 2048) ||
+            (ctx->DrawBuffer->Height + draw_y > 2048));
    /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
    if (draw_offset != i915->last_draw_offset) {
-      FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
-               (ctx->DrawBuffer->Width + draw_x > 2048) ||
-               (ctx->DrawBuffer->Height + draw_y > 2048));
-
       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
       i915->last_draw_offset = draw_offset;
    } else
@@ -804,14 +806,10 @@ i915_update_draw_buffer(struct intel_context *intel)
                                fb->_NumColorDrawBuffers);
    intel->NewGLState |= _NEW_BUFFERS;
 
-   /* update viewport since it depends on window size */
-   intelCalcViewport(ctx);
-
    /* Set state we know depends on drawable parameters:
     */
-   ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
-                      ctx->Scissor.Width, ctx->Scissor.Height);
-   ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far);
+   intelCalcViewport(ctx);
+   ctx->Driver.Scissor(ctx);
 
    /* Update culling direction which changes depending on the
     * orientation of the buffer:
@@ -845,14 +843,6 @@ i915_assert_not_dirty( struct intel_context *intel )
    (void) dirty;
 }
 
-/** Return false; i915 does not support HiZ. */
-static bool
-i915_is_hiz_depth_format(struct intel_context *intel,
-                         gl_format format)
-{
-   return false;
-}
-
 static void
 i915_invalidate_state(struct intel_context *intel, GLuint new_state)
 {
@@ -880,5 +870,4 @@ i915InitVtbl(struct i915_context *i915)
    i915->intel.vtbl.finish_batch = intel_finish_vb;
    i915->intel.vtbl.invalidate_state = i915_invalidate_state;
    i915->intel.vtbl.render_target_supported = i915_render_target_supported;
-   i915->intel.vtbl.is_hiz_depth_format = i915_is_hiz_depth_format;
 }