/**************************************************************************
*
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2003 VMware, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
}
}
-/**
- * Emits the packet for switching the blitter from X to Y tiled or back.
- *
- * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
- * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
- * part of the power context, not a render context, and if the batchbuffer was
- * to get flushed between setting and blitting, or blitting and restoring, our
- * tiling state would leak into other unsuspecting applications (like the X
- * server).
- */
-static void
-set_blitter_tiling(struct intel_context *intel,
- bool dst_y_tiled, bool src_y_tiled)
-{
- assert(intel->gen >= 6);
-
- /* Idle the blitter before we update how tiling is interpreted. */
- OUT_BATCH(MI_FLUSH_DW);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(BCS_SWCTRL);
- OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
- (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
- (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
-}
-
-#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do { \
- BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
- if (dst_y_tiled || src_y_tiled) \
- set_blitter_tiling(intel, dst_y_tiled, src_y_tiled); \
- } while (0)
-
-#define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do { \
- if (dst_y_tiled || src_y_tiled) \
- set_blitter_tiling(intel, false, false); \
- ADVANCE_BATCH(); \
- } while (0)
-
/**
* Implements a rectangular block transfer (blit) of pixels between two
* miptrees.
* consistent with what we want in the callers (glCopyTexSubImage(),
* glBlitFramebuffer(), texture validation, etc.).
*/
- gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
- gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
+ mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
+ mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
/* The blitter doesn't support doing any format conversions. We do also
* support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
* channel to 1.0 at the end.
*/
if (src_format != dst_format &&
- ((src_format != MESA_FORMAT_ARGB8888 &&
- src_format != MESA_FORMAT_XRGB8888) ||
- (dst_format != MESA_FORMAT_ARGB8888 &&
- dst_format != MESA_FORMAT_XRGB8888))) {
+ ((src_format != MESA_FORMAT_B8G8R8A8_UNORM &&
+ src_format != MESA_FORMAT_B8G8R8X8_UNORM) ||
+ (dst_format != MESA_FORMAT_B8G8R8A8_UNORM &&
+ dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) {
perf_debug("%s: Can't use hardware blitter from %s to %s, "
"falling back.\n", __FUNCTION__,
_mesa_get_format_name(src_format),
return false;
}
- if (src_mt->format == MESA_FORMAT_XRGB8888 &&
- dst_mt->format == MESA_FORMAT_ARGB8888) {
+ if (src_mt->format == MESA_FORMAT_B8G8R8X8_UNORM &&
+ dst_mt->format == MESA_FORMAT_B8G8R8A8_UNORM) {
intel_miptree_set_alpha_to_one(intel, dst_mt,
dst_x, dst_y,
width, height);
if (src_offset & 4095)
return false;
}
- if ((dst_y_tiled || src_y_tiled) && intel->gen < 6)
+ if (dst_y_tiled || src_y_tiled)
return false;
/* do space check before going any further */
if (pass >= 2)
return false;
- intel_batchbuffer_require_space(intel, 8 * 4, true);
+ intel_batchbuffer_require_space(intel, 8 * 4);
DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
__FUNCTION__,
src_buffer, src_pitch, src_offset, src_x, src_y,
assert(dst_x < dst_x2);
assert(dst_y < dst_y2);
- BEGIN_BATCH_BLT_TILED(8, dst_y_tiled, src_y_tiled);
+ BEGIN_BATCH(8);
OUT_BATCH(CMD | (8 - 2));
OUT_BATCH(BR13 | (uint16_t)dst_pitch);
I915_GEM_DOMAIN_RENDER, 0,
src_offset);
- ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
+ ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel);
_mesa_unclamped_float_rgba_to_ubyte(clear, color);
switch (intel_rb_format(irb)) {
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
+ case MESA_FORMAT_B8G8R8A8_UNORM:
+ case MESA_FORMAT_B8G8R8X8_UNORM:
clear_val = PACK_COLOR_8888(clear[3], clear[0],
clear[1], clear[2]);
break;
clear_val = PACK_COLOR_1555(clear[3], clear[0],
clear[1], clear[2]);
break;
- case MESA_FORMAT_A8:
+ case MESA_FORMAT_A_UNORM8:
clear_val = PACK_COLOR_8888(clear[3], clear[3],
clear[3], clear[3]);
break;
intel_batchbuffer_flush(intel);
}
- BEGIN_BATCH_BLT(6);
+ BEGIN_BATCH(6);
OUT_BATCH(CMD | (6 - 2));
OUT_BATCH(BR13);
OUT_BATCH((y1 << 16) | x1);
return false;
}
- assert( logic_op - GL_CLEAR >= 0 );
- assert( logic_op - GL_CLEAR < 0x10 );
+ assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
assert(dst_pitch > 0);
if (w < 0 || h < 0)
intel_batchbuffer_require_space(intel,
(8 * 4) +
(3 * 4) +
- dwords * 4, true);
+ dwords * 4);
opcode = XY_SETUP_BLT_CMD;
if (cpp == 4)
if (dst_tiling != I915_TILING_NONE)
blit_cmd |= XY_DST_TILED;
- BEGIN_BATCH_BLT(8 + 3);
+ BEGIN_BATCH(8 + 3);
OUT_BATCH(opcode | (8 - 2));
OUT_BATCH(br13);
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
OUT_BATCH(((y + h) << 16) | (x + w));
ADVANCE_BATCH();
- intel_batchbuffer_data(intel, src_bits, dwords * 4, true);
+ intel_batchbuffer_data(intel, src_bits, dwords * 4);
intel_batchbuffer_emit_mi_flush(intel);
intel_batchbuffer_flush(intel);
}
- bool dst_y_tiled = region->tiling == I915_TILING_Y;
-
- BEGIN_BATCH_BLT_TILED(6, dst_y_tiled, false);
+ BEGIN_BATCH(6);
OUT_BATCH(CMD | (6 - 2));
OUT_BATCH(BR13);
OUT_BATCH((y << 16) | x);
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
- ADVANCE_BATCH_TILED(dst_y_tiled, false);
+ ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel);
}
projects / mesa.git / blobdiff