i965/gs: Add GS_OPCODE_SET_DWORD_2_IMMED.

[mesa.git] / src / mesa / drivers / dri / i915 / intel_context.h

diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h
index 1c8c87ddb33f13ec61381a06617feff2c5f3b843..6edb1895d9cbbf5fb2a607153267dd0374459780 100644 (file)
--- a/src/mesa/drivers/dri/i915/intel_context.h
+++ b/src/mesa/drivers/dri/i915/intel_context.h
@@ -95,8 +95,6 @@ extern void intelFallback(struct intel_context *intel, GLbitfield bit,
 #define INTEL_WRITE_FULL  0x2
 #define INTEL_READ        0x4
 
-#define INTEL_MAX_FIXUP 64
-
 #ifndef likely
 #ifdef __GNUC__
 #define likely(expr) (__builtin_expect(expr, 1))
@@ -114,33 +112,17 @@ struct intel_sync_object {
    drm_intel_bo *bo;
 };
 
-struct brw_context;
-
 struct intel_batchbuffer {
    /** Current batchbuffer being queued up. */
    drm_intel_bo *bo;
    /** Last BO submitted to the hardware.  Used for glFinish(). */
    drm_intel_bo *last_bo;
-   /** BO for post-sync nonzero writes for gen6 workaround. */
-   drm_intel_bo *workaround_bo;
-   bool need_workaround_flush;
-
-   struct cached_batch_item *cached_items;
 
    uint16_t emit, total;
    uint16_t used, reserved_space;
    uint32_t *map;
    uint32_t *cpu_map;
 #define BATCH_SZ (8192*sizeof(uint32_t))
-
-   uint32_t state_batch_offset;
-   bool is_blit;
-   bool needs_sol_reset;
-
-   struct {
-      uint16_t used;
-      int reloc_count;
-   } saved;
 };
 
 /**
@@ -181,28 +163,6 @@ struct intel_context
       void (*annotate_aub)(struct intel_context *intel);
       bool (*render_target_supported)(struct intel_context *intel,
                                      struct gl_renderbuffer *rb);
-
-      /**
-       * Surface state operations (i965+ only)
-       * \{
-       */
-      void (*update_texture_surface)(struct gl_context *ctx,
-                                     unsigned unit,
-                                     uint32_t *binding_table,
-                                     unsigned surf_index);
-      void (*update_renderbuffer_surface)(struct brw_context *brw,
-                                         struct gl_renderbuffer *rb,
-                                         bool layered,
-                                         unsigned unit);
-      void (*update_null_renderbuffer_surface)(struct brw_context *brw,
-                                              unsigned unit);
-      void (*create_constant_surface)(struct brw_context *brw,
-                                     drm_intel_bo *bo,
-                                     uint32_t offset,
-                                     uint32_t size,
-                                     uint32_t *out_offset,
-                                      bool dword_pitch);
-      /** \} */
    } vtbl;
 
    GLbitfield Fallback;  /**< mask of INTEL_FALLBACK_x bits */
@@ -215,19 +175,9 @@ struct intel_context
     * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
     */
    int gen;
-   int gt;
-   bool needs_ff_sync;
-   bool is_haswell;
-   bool is_baytrail;
-   bool is_g4x;
    bool is_945;
-   bool has_llc;
    bool has_swizzling;
 
-   int urb_size;
-
-   drm_intel_context *hw_ctx;
-
    struct intel_batchbuffer batch;
 
    drm_intel_bo *first_post_swapbuffers_batch;
@@ -265,8 +215,6 @@ struct intel_context
 
    uint32_t max_gtt_map_object_size;
 
-   GLuint stats_wm;
-
    /* Offsets of fields within the current vertex:
     */
    GLuint coloroffset;
@@ -412,7 +360,6 @@ extern int INTEL_DEBUG;
 
 #define DEBUG_TEXTURE  0x1
 #define DEBUG_STATE    0x2
-#define DEBUG_IOCTL    0x4
 #define DEBUG_BLIT     0x8
 #define DEBUG_MIPTREE   0x10
 #define DEBUG_PERF     0x20
@@ -421,21 +368,11 @@ extern int INTEL_DEBUG;
 #define DEBUG_BUFMGR    0x200
 #define DEBUG_REGION    0x400
 #define DEBUG_FBO       0x800
-#define DEBUG_GS        0x1000
 #define DEBUG_SYNC     0x2000
-#define DEBUG_PRIMS    0x4000
-#define DEBUG_VERTS    0x8000
 #define DEBUG_DRI       0x10000
-#define DEBUG_SF        0x20000
 #define DEBUG_STATS     0x100000
 #define DEBUG_WM        0x400000
-#define DEBUG_URB       0x800000
-#define DEBUG_VS        0x1000000
-#define DEBUG_CLIP      0x2000000
 #define DEBUG_AUB       0x4000000
-#define DEBUG_SHADER_TIME 0x8000000
-#define DEBUG_BLORP     0x10000000
-#define DEBUG_NO16      0x20000000
 
 #ifdef HAVE_ANDROID_PLATFORM
 #define LOG_TAG "INTEL-MESA"
@@ -480,20 +417,6 @@ extern int INTEL_DEBUG;
    }                                                            \
 } while (0)
 
-#define PCI_CHIP_845_G                 0x2562
-#define PCI_CHIP_I830_M                        0x3577
-#define PCI_CHIP_I855_GM               0x3582
-#define PCI_CHIP_I865_G                        0x2572
-#define PCI_CHIP_I915_G                        0x2582
-#define PCI_CHIP_I915_GM               0x2592
-#define PCI_CHIP_I945_G                        0x2772
-#define PCI_CHIP_I945_GM               0x27A2
-#define PCI_CHIP_I945_GME              0x27AE
-#define PCI_CHIP_G33_G                 0x29C2
-#define PCI_CHIP_Q35_G                 0x29B2
-#define PCI_CHIP_Q33_G                 0x29D2
-
-
 /* ================================================================
  * intel_context.c:
  */