/**************************************************************************
*
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2003 VMware, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define INTEL_WRITE_FULL 0x2
#define INTEL_READ 0x4
-#define INTEL_MAX_FIXUP 64
-
#ifndef likely
#ifdef __GNUC__
#define likely(expr) (__builtin_expect(expr, 1))
drm_intel_bo *bo;
};
-struct brw_context;
-
struct intel_batchbuffer {
/** Current batchbuffer being queued up. */
drm_intel_bo *bo;
uint32_t *map;
uint32_t *cpu_map;
#define BATCH_SZ (8192*sizeof(uint32_t))
-
- uint32_t state_batch_offset;
- bool is_blit;
- bool needs_sol_reset;
};
/**
void (*annotate_aub)(struct intel_context *intel);
bool (*render_target_supported)(struct intel_context *intel,
struct gl_renderbuffer *rb);
-
- /**
- * Surface state operations (i965+ only)
- * \{
- */
- void (*update_texture_surface)(struct gl_context *ctx,
- unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index);
- void (*update_renderbuffer_surface)(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned unit);
- void (*update_null_renderbuffer_surface)(struct brw_context *brw,
- unsigned unit);
- void (*create_constant_surface)(struct brw_context *brw,
- drm_intel_bo *bo,
- uint32_t offset,
- uint32_t size,
- uint32_t *out_offset,
- bool dword_pitch);
- /** \} */
} vtbl;
GLbitfield Fallback; /**< mask of INTEL_FALLBACK_x bits */
* Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
*/
int gen;
- int gt;
- bool is_haswell;
- bool is_baytrail;
- bool is_g4x;
bool is_945;
- bool has_llc;
bool has_swizzling;
- int urb_size;
-
- drm_intel_context *hw_ctx;
-
struct intel_batchbuffer batch;
drm_intel_bo *first_post_swapbuffers_batch;
uint32_t max_gtt_map_object_size;
- GLuint stats_wm;
-
/* Offsets of fields within the current vertex:
*/
GLuint coloroffset;
__DRIcontext *driContext;
struct intel_screen *intelScreen;
- void (*saved_viewport)(struct gl_context * ctx,
- GLint x, GLint y, GLsizei width, GLsizei height);
/**
* Configuration cache
#define SUBPIXEL_X 0.125
#define SUBPIXEL_Y 0.125
-/**
- * Align a value down to an alignment value
- *
- * If \c value is not already aligned to the requested alignment value, it
- * will be rounded down.
- *
- * \param value Value to be rounded
- * \param alignment Alignment value to be used. This must be a power of two.
- *
- * \sa ALIGN()
- */
-#define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
-
-static INLINE uint32_t
-U_FIXED(float value, uint32_t frac_bits)
-{
- value *= (1 << frac_bits);
- return value < 0 ? 0 : value;
-}
-
-static INLINE uint32_t
-S_FIXED(float value, uint32_t frac_bits)
-{
- return value * (1 << frac_bits);
-}
-
#define INTEL_FIREVERTICES(intel) \
do { \
if ((intel)->prim.flush) \
#define DEBUG_TEXTURE 0x1
#define DEBUG_STATE 0x2
-#define DEBUG_IOCTL 0x4
#define DEBUG_BLIT 0x8
#define DEBUG_MIPTREE 0x10
#define DEBUG_PERF 0x20
#define DEBUG_BUFMGR 0x200
#define DEBUG_REGION 0x400
#define DEBUG_FBO 0x800
-#define DEBUG_GS 0x1000
#define DEBUG_SYNC 0x2000
-#define DEBUG_PRIMS 0x4000
-#define DEBUG_VERTS 0x8000
#define DEBUG_DRI 0x10000
-#define DEBUG_SF 0x20000
#define DEBUG_STATS 0x100000
#define DEBUG_WM 0x400000
-#define DEBUG_URB 0x800000
-#define DEBUG_VS 0x1000000
-#define DEBUG_CLIP 0x2000000
#define DEBUG_AUB 0x4000000
-#define DEBUG_BLORP 0x10000000
-#define DEBUG_NO16 0x20000000
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG "INTEL-MESA"
} \
} while (0)
-#define PCI_CHIP_845_G 0x2562
-#define PCI_CHIP_I830_M 0x3577
-#define PCI_CHIP_I855_GM 0x3582
-#define PCI_CHIP_I865_G 0x2572
-#define PCI_CHIP_I915_G 0x2582
-#define PCI_CHIP_I915_GM 0x2592
-#define PCI_CHIP_I945_G 0x2772
-#define PCI_CHIP_I945_GM 0x27A2
-#define PCI_CHIP_I945_GME 0x27AE
-#define PCI_CHIP_G33_G 0x29C2
-#define PCI_CHIP_Q35_G 0x29B2
-#define PCI_CHIP_Q33_G 0x29D2
-
-
/* ================================================================
* intel_context.c:
*/
+extern const char *const i915_vendor_string;
+
+extern const char *i915_get_renderer_string(unsigned deviceID);
+
extern bool intelInitContext(struct intel_context *intel,
int api,
unsigned major_version,
unsigned minor_version,
+ uint32_t flags,
const struct gl_config * mesaVis,
__DRIcontext * driContextPriv,
void *sharedContextPrivate,
projects / mesa.git / blobdiff