#include <errno.h>
#include <time.h>
#include <unistd.h>
+#include "drm-uapi/drm_fourcc.h"
#include "main/glheader.h"
#include "main/context.h"
#include "main/framebuffer.h"
#include "swrast/s_renderbuffer.h"
#include "utils.h"
-#include "xmlpool.h"
+#include "util/xmlpool.h"
+#include "util/u_memory.h"
static const __DRIconfigOptionsExtension i915_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
- DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC)
/* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
* DRI_CONF_BO_REUSE_ALL
*/
DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1")
- DRI_CONF_DESC_BEGIN(en, "Buffer object reuse")
+ DRI_CONF_DESC_BEGIN("Buffer object reuse")
DRI_CONF_ENUM(0, "Disable buffer object reuse")
DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
DRI_CONF_DESC_END
DRI_CONF_OPT_END
- DRI_CONF_OPT_BEGIN_B(early_z, "false")
- DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 945-only).")
+ DRI_CONF_OPT_BEGIN_B(fragment_shader, "true")
+ DRI_CONF_DESC("Enable limited ARB_fragment_shader support on 915/945.")
DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
- DRI_CONF_FORCE_S3TC_ENABLE("false")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
- DRI_CONF_NO_RAST("false")
DRI_CONF_ALWAYS_FLUSH_BATCH("false")
DRI_CONF_ALWAYS_FLUSH_CACHE("false")
DRI_CONF_DISABLE_THROTTLING("false")
DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
+ DRI_CONF_OPT_BEGIN_B(stub_occlusion_query, "false")
+ DRI_CONF_DESC("Enable stub ARB_occlusion_query support on 915/945.")
+ DRI_CONF_OPT_END
+
DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
- DRI_CONF_DESC(en, "Perform code generation at shader link time.")
+ DRI_CONF_DESC("Perform code generation at shader link time.")
DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_END
#include "intel_tex.h"
#include "intel_regions.h"
-#include "i915_drm.h"
-
-#ifdef USE_NEW_INTERFACE
-static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
-#endif /*USE_NEW_INTERFACE */
+#include "drm-uapi/i915_drm.h"
/**
* For debugging purposes, this returns a time in seconds.
}
static const __DRItexBufferExtension intelTexBufferExtension = {
- .base = { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
+ .base = { __DRI_TEX_BUFFER, 3 },
.setTexBuffer = intelSetTexBuffer,
.setTexBuffer2 = intelSetTexBuffer2,
};
static struct intel_image_format intel_image_formats[] = {
- { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { DRM_FORMAT_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
{ __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
- { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { DRM_FORMAT_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } },
- { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { DRM_FORMAT_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
- { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { DRM_FORMAT_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
- /* For YUYV buffers, we set up two overlapping DRI images and treat
- * them as planar buffers in the compositors. Plane 0 is GR88 and
- * samples YU or YV pairs and places Y into the R component, while
- * plane 1 is ARGB and samples YUYV clusters and places pairs and
- * places U into the G component and V into A. This lets the
- * texture sampler interpolate the Y components correctly when
- * sampling from plane 0, and interpolate U and V correctly when
- * sampling from plane 1. */
- { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
+ /* For YUYV and UYVY buffers, we set up two overlapping DRI images
+ * and treat them as planar buffers in the compositors.
+ * Plane 0 is GR88 and samples YU or YV pairs and places Y into
+ * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
+ * clusters and places pairs and places U into the G component and
+ * V into A. This lets the texture sampler interpolate the Y
+ * components correctly when sampling from plane 0, and interpolate
+ * U and V correctly when sampling from plane 1. */
+ { DRM_FORMAT_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
- { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }
+ { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
+ { DRM_FORMAT_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
+ { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }
};
static __DRIimage *
intel_miptree_check_level_layer(mt, level, zoffset);
- intel_region_get_tile_masks(mt->region, &mask_x, &mask_y, false);
+ intel_region_get_tile_masks(mt->region, &mask_x, &mask_y);
intel_miptree_get_image_offset(mt, level, zoffset, &draw_x, &draw_y);
image->width = mt->level[level].width;
image->offset = intel_region_get_aligned_offset(mt->region,
draw_x & ~mask_x,
- draw_y & ~mask_y,
- false);
+ draw_y & ~mask_y);
intel_region_reference(&image->region, mt->region);
}
image->data = loaderPrivate;
intel_setup_image_from_mipmap_tree(intel, image, iobj->mt, level, zoffset);
image->dri_format = driGLFormatToImageFormat(image->format);
- if (image->dri_format == MESA_FORMAT_NONE) {
+ if (image->dri_format == __DRI_IMAGE_FORMAT_NONE) {
*error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
free(image);
return NULL;
*value = image->planar_format->components;
return true;
case __DRI_IMAGE_ATTRIB_FD:
- if (drm_intel_bo_gem_export_to_prime(image->region->bo, value) == 0)
- return true;
- return false;
+ return !drm_intel_bo_gem_export_to_prime(image->region->bo, value);
default:
return false;
}
return NULL;
}
+ intel_setup_image_from_dimensions(image);
+
image->planar_format = f;
for (i = 0; i < f->nplanes; i++) {
index = f->planes[i].buffer_index;
image->offset = offset;
intel_setup_image_from_dimensions(image);
- intel_region_get_tile_masks(image->region, &mask_x, &mask_y, false);
+ intel_region_get_tile_masks(image->region, &mask_x, &mask_y);
if (offset & mask_x)
_mesa_warning(NULL,
"intel_create_sub_image: offset not on tile boundary");
return image;
}
-static struct __DRIimageExtensionRec intelImageExtension = {
+static const __DRIimageExtension intelImageExtension = {
.base = { __DRI_IMAGE, 7 },
.createImageFromName = intel_create_image_from_name,
* (uint64_t) system_page_size;
const unsigned system_memory_megabytes =
- (unsigned) (system_memory_bytes / 1024);
+ (unsigned) (system_memory_bytes / (1024 * 1024));
value[0] = MIN2(system_memory_megabytes, gpu_mappable_megabytes);
return 0;
case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE:
value[0] = 1;
return 0;
- case __DRI2_RENDERER_PREFERRED_PROFILE:
- value[0] = (1U << __DRI_API_OPENGL);
+ case __DRI2_RENDERER_HAS_TEXTURE_3D:
+ value[0] = 1;
return 0;
default:
return driQueryRendererIntegerCommon(psp, param, value);
return -1;
}
-static struct __DRI2rendererQueryExtensionRec intelRendererQueryExtension = {
+static const __DRI2rendererQueryExtension intelRendererQueryExtension = {
.base = { __DRI2_RENDERER_QUERY, 1 },
.queryInteger = i915_query_renderer_integer,
static const __DRIextension *intelScreenExtensions[] = {
&intelTexBufferExtension.base,
+ &intelFenceExtension.base,
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
&dri2ConfigQueryExtension.base,
+ &dri2NoErrorExtension.base,
NULL
};
/* setup the hardware-based renderbuffers */
rb = intel_create_renderbuffer(rgbFormat);
- _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
+ _mesa_attach_and_own_rb(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
if (mesaVis->doubleBufferMode) {
rb = intel_create_renderbuffer(rgbFormat);
- _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
+ _mesa_attach_and_own_rb(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
}
/*
* Use combined depth/stencil. Note that the renderbuffer is
* attached to two attachment points.
*/
- rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
+ rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT);
+ _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_attach_and_reference_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
}
else if (mesaVis->depthBits == 16) {
assert(mesaVis->stencilBits == 0);
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
}
else {
assert(mesaVis->depthBits == 0);
static GLboolean
intelCreateContext(gl_api api,
- const struct gl_config * mesaVis,
+ const struct gl_config * mesaVis,
__DRIcontext * driContextPriv,
- unsigned major_version,
- unsigned minor_version,
- uint32_t flags,
- bool notify_reset,
- unsigned *error,
+ const struct __DriverContextConfig *ctx_config,
+ unsigned *error,
void *sharedContextPrivate)
{
bool success = false;
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
struct intel_screen *intelScreen = sPriv->driverPrivate;
- if (flags & ~__DRI_CTX_FLAG_DEBUG) {
+ if (ctx_config->flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
return false;
}
- if (notify_reset) {
+ if (ctx_config->attribute_mask) {
*error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
return false;
}
- if (IS_9XX(intelScreen->deviceID)) {
+ if (IS_GEN3(intelScreen->deviceID)) {
success = i915CreateContext(api, mesaVis, driContextPriv,
- major_version, minor_version, flags,
+ ctx_config->major_version,
+ ctx_config->minor_version,
+ ctx_config->flags,
error, sharedContextPrivate);
} else {
intelScreen->no_vbo = true;
success = i830CreateContext(api, mesaVis, driContextPriv,
- major_version, minor_version, flags,
+ ctx_config->major_version,
+ ctx_config->minor_version,
+ ctx_config->flags,
error, sharedContextPrivate);
}
return true;
}
-static bool
-intel_detect_swizzling(struct intel_screen *screen)
-{
- drm_intel_bo *buffer;
- unsigned long flags = 0;
- unsigned long aligned_pitch;
- uint32_t tiling = I915_TILING_X;
- uint32_t swizzle_mode = 0;
-
- buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "swizzle test",
- 64, 64, 4,
- &tiling, &aligned_pitch, flags);
- if (buffer == NULL)
- return false;
-
- drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode);
- drm_intel_bo_unreference(buffer);
-
- if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE)
- return false;
- else
- return true;
-}
-
static __DRIconfig**
intel_screen_make_configs(__DRIscreen *dri_screen)
{
static const mesa_format formats[] = {
MESA_FORMAT_B5G6R5_UNORM,
- MESA_FORMAT_B8G8R8A8_UNORM
+ MESA_FORMAT_B8G8R8A8_UNORM,
+ MESA_FORMAT_B8G8R8X8_UNORM
};
- /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
+ /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
static const GLenum back_buffer_modes[] = {
- GLX_SWAP_UNDEFINED_OML, GLX_NONE,
+ __DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE
};
static const uint8_t singlesample_samples[1] = {0};
num_depth_stencil_bits,
back_buffer_modes, 2,
singlesample_samples, 1,
- false);
+ false, false, false);
configs = driConcatConfigs(configs, new_configs);
}
depth_bits, stencil_bits, 1,
back_buffer_modes, 1,
singlesample_samples, 1,
- true);
+ true, false, false);
configs = driConcatConfigs(configs, new_configs);
}
__DRIscreen *psp = screen->driScrnPriv;
switch (screen->gen) {
- case 3:
+ case 3: {
+ bool has_fragment_shader = driQueryOptionb(&screen->optionCache, "fragment_shader");
+ bool has_occlusion_query = driQueryOptionb(&screen->optionCache, "stub_occlusion_query");
+
psp->max_gl_core_version = 0;
psp->max_gl_es1_version = 11;
- psp->max_gl_compat_version = 21;
psp->max_gl_es2_version = 20;
+
+ if (has_fragment_shader && has_occlusion_query) {
+ psp->max_gl_compat_version = 21;
+ } else {
+ psp->max_gl_compat_version = 14;
+ }
break;
+ }
case 2:
psp->max_gl_core_version = 0;
psp->max_gl_compat_version = 13;
{
struct intel_screen *intelScreen;
- if (psp->dri2.loader->base.version <= 2 ||
+ if (psp->image.loader) {
+ } else if (psp->dri2.loader->base.version <= 2 ||
psp->dri2.loader->getBuffersWithFormat == NULL) {
fprintf(stderr,
"\nERROR! DRI2 loader with getBuffersWithFormat() "
intelScreen->deviceID = drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr);
- if (IS_9XX(intelScreen->deviceID)) {
+ if (IS_GEN3(intelScreen->deviceID)) {
intelScreen->gen = 3;
} else {
intelScreen->gen = 2;
}
- intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen);
-
set_max_gl_versions(intelScreen);
psp->extensions = intelScreenExtensions;
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