fix up radeon span functions using latest r200 code from Brian,
[mesa.git] / src / mesa / drivers / dri / i915 / intel_tex.c
index 5fc904e601c1259b3a23c6421735d4b4f93d1f2c..d256dbf7cb833fc620c4970943601a3bcad4e8e0 100644 (file)
@@ -453,7 +453,7 @@ intelChooseTextureFormat( GLcontext *ctx, GLint internalFormat,
 {
    intelContextPtr intel = INTEL_CONTEXT( ctx );
    const GLboolean do32bpt = ( intel->intelScreen->cpp == 4 &&
-                              intel->intelScreen->textureSize > 4*1024*1024);
+                              intel->intelScreen->tex.size > 4*1024*1024);
 
    switch ( internalFormat ) {
    case 4:
@@ -646,8 +646,7 @@ static void intelUploadTexImage( intelContextPtr intel,
                 image->Width, image->Height, image->Depth, offset,
                 row_len, t->Pitch, t->depth_pitch);
 
-      switch(image->IntFormat)
-       {
+      switch (image->InternalFormat) {
        case GL_COMPRESSED_RGB_FXT1_3DFX:
        case GL_COMPRESSED_RGBA_FXT1_3DFX:
        case GL_RGB_S3TC:
@@ -669,9 +668,9 @@ static void intelUploadTexImage( intelContextPtr intel,
          }
          break;
        default:
-         fprintf(stderr,"Internal Compressed format not supported %d\n", image->IntFormat);
+         fprintf(stderr,"Internal Compressed format not supported %d\n", image->InternalFormat);
          break;
-       }
+      }
    }
    else {
       GLuint row_len = image->Width * image->TexFormat->TexelBytes;
@@ -749,7 +748,7 @@ int intelUploadTexImages( intelContextPtr intel,
 
         /* Set the base offset of the texture image */
         t->BufAddr = intel->intelScreen->tex.map + t->base.memBlock->ofs;
-        t->TextureOffset = intel->intelScreen->textureOffset + t->base.memBlock->ofs;
+        t->TextureOffset = intel->intelScreen->tex.offset + t->base.memBlock->ofs;
         t->dirty = ~0;
       }