i965/vec4: Don't lose the force_writemask_all flag during CSE.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_binding_tables.c

diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 1cd4bba6753c54eb1fb2cca562380af8b2729385..08e419144283ffb976de3ea892382e2ad761f9a0 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -56,21 +56,23 @@ brw_upload_binding_table(struct brw_context *brw,
                          GLbitfield brw_new_binding_table,
                          struct brw_stage_state *stage_state)
 {
-   /* CACHE_NEW_*_PROG */
+   /* BRW_NEW_*_PROG_DATA */
    struct brw_stage_prog_data *prog_data = stage_state->prog_data;
 
    if (prog_data->binding_table.size_bytes == 0) {
       /* There are no surfaces; skip making the binding table altogether. */
-      if (stage_state->bind_bo_offset == 0)
+      if (stage_state->bind_bo_offset == 0 && brw->gen < 9)
          return;
 
       stage_state->bind_bo_offset = 0;
    } else {
       /* Upload a new binding table. */
       if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
-         brw->vtbl.create_raw_surface(
-            brw, brw->shader_time.bo, 0, brw->shader_time.bo->size,
-            &stage_state->surf_offset[prog_data->binding_table.shader_time_start], true);
+         brw->vtbl.emit_buffer_surface_state(
+            brw, &stage_state->surf_offset[
+                    prog_data->binding_table.shader_time_start],
+            brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW,
+            brw->shader_time.bo->size, 1, true);
       }
 
       uint32_t *bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
@@ -111,8 +113,8 @@ const struct brw_tracked_state brw_vs_binding_table = {
       .mesa = 0,
       .brw = BRW_NEW_BATCH |
              BRW_NEW_VS_CONSTBUF |
+             BRW_NEW_VS_PROG_DATA |
              BRW_NEW_SURFACES,
-      .cache = CACHE_NEW_VS_PROG
    },
    .emit = brw_vs_upload_binding_table,
 };
@@ -130,8 +132,9 @@ brw_upload_wm_binding_table(struct brw_context *brw)
 const struct brw_tracked_state brw_wm_binding_table = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH | BRW_NEW_SURFACES,
-      .cache = CACHE_NEW_WM_PROG
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_FS_PROG_DATA |
+             BRW_NEW_SURFACES,
    },
    .emit = brw_upload_wm_binding_table,
 };
@@ -154,8 +157,8 @@ const struct brw_tracked_state brw_gs_binding_table = {
       .mesa = 0,
       .brw = BRW_NEW_BATCH |
              BRW_NEW_GS_CONSTBUF |
+             BRW_NEW_GS_PROG_DATA |
              BRW_NEW_SURFACES,
-      .cache = CACHE_NEW_GS_PROG
    },
    .emit = brw_gs_upload_binding_table,
 };
@@ -189,12 +192,11 @@ gen4_upload_binding_table_pointers(struct brw_context *brw)
 const struct brw_tracked_state brw_binding_table_pointers = {
    .dirty = {
       .mesa = 0,
-      .brw = (BRW_NEW_BATCH |
-              BRW_NEW_STATE_BASE_ADDRESS |
-              BRW_NEW_VS_BINDING_TABLE |
-              BRW_NEW_GS_BINDING_TABLE |
-              BRW_NEW_PS_BINDING_TABLE),
-      .cache = 0,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_GS_BINDING_TABLE |
+             BRW_NEW_PS_BINDING_TABLE |
+             BRW_NEW_STATE_BASE_ADDRESS |
+             BRW_NEW_VS_BINDING_TABLE,
    },
    .emit = gen4_upload_binding_table_pointers,
 };
@@ -215,7 +217,10 @@ gen6_upload_binding_table_pointers(struct brw_context *brw)
              GEN6_BINDING_TABLE_MODIFY_PS |
              (4 - 2));
    OUT_BATCH(brw->vs.base.bind_bo_offset); /* vs */
-   OUT_BATCH(brw->ff_gs.bind_bo_offset); /* gs */
+   if (brw->ff_gs.prog_active)
+      OUT_BATCH(brw->ff_gs.bind_bo_offset); /* gs */
+   else
+      OUT_BATCH(brw->gs.base.bind_bo_offset); /* gs */
    OUT_BATCH(brw->wm.base.bind_bo_offset); /* wm/ps */
    ADVANCE_BATCH();
 }
@@ -223,16 +228,13 @@ gen6_upload_binding_table_pointers(struct brw_context *brw)
 const struct brw_tracked_state gen6_binding_table_pointers = {
    .dirty = {
       .mesa = 0,
-      .brw = (BRW_NEW_BATCH |
-              BRW_NEW_STATE_BASE_ADDRESS |
-              BRW_NEW_VS_BINDING_TABLE |
-              BRW_NEW_GS_BINDING_TABLE |
-              BRW_NEW_PS_BINDING_TABLE),
-      .cache = 0,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_GS_BINDING_TABLE |
+             BRW_NEW_PS_BINDING_TABLE |
+             BRW_NEW_STATE_BASE_ADDRESS |
+             BRW_NEW_VS_BINDING_TABLE,
    },
    .emit = gen6_upload_binding_table_pointers,
 };
 
-/* Gen7+ code lives in gen7_{vs,gs,wm}_state.c. */
-
 /** @} */