i965: Convert brw->*_program into a brw->programs[i] array.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_binding_tables.c
index 6769f0cd1abd235cec0f9e70b3e905c0597ee057..73f5e56010b41f2f6a1a1b8e6c7949b0b8837e84 100644 (file)
 void
 brw_upload_binding_table(struct brw_context *brw,
                          uint32_t packet_name,
-                         GLbitfield brw_new_binding_table,
                          const struct brw_stage_prog_data *prog_data,
                          struct brw_stage_state *stage_state)
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
    if (prog_data->binding_table.size_bytes == 0) {
       /* There are no surfaces; skip making the binding table altogether. */
-      if (stage_state->bind_bo_offset == 0 && brw->gen < 9)
+      if (stage_state->bind_bo_offset == 0 && devinfo->gen < 9)
          return;
 
       stage_state->bind_bo_offset = 0;
    } else {
       /* Upload a new binding table. */
       if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
-         brw->vtbl.emit_buffer_surface_state(
+         brw_emit_buffer_surface_state(
             brw, &stage_state->surf_offset[
                     prog_data->binding_table.shader_time_start],
-            brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW,
-            brw->shader_time.bo->size, 1, true);
+            brw->shader_time.bo, 0, ISL_FORMAT_RAW,
+            brw->shader_time.bo->size, 1, RELOC_WRITE);
       }
-
-      uint32_t *bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
-                                       prog_data->binding_table.size_bytes, 32,
-                                       &stage_state->bind_bo_offset);
+      uint32_t *bind =
+         brw_state_batch(brw, prog_data->binding_table.size_bytes,
+                         32, &stage_state->bind_bo_offset);
 
       /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
       memcpy(bind, stage_state->surf_offset,
              prog_data->binding_table.size_bytes);
    }
 
-   brw->ctx.NewDriverState |= brw_new_binding_table;
+   brw->ctx.NewDriverState |= BRW_NEW_BINDING_TABLE_POINTERS;
 
-   if (brw->gen >= 7) {
+   if (devinfo->gen >= 7) {
       BEGIN_BATCH(2);
       OUT_BATCH(packet_name << 16 | (2 - 2));
+      /* Align SurfaceStateOffset[16:6] format to [15:5] PS Binding Table field
+       * when hw-generated binding table is enabled.
+       */
       OUT_BATCH(stage_state->bind_bo_offset);
       ADVANCE_BATCH();
    }
@@ -105,7 +108,7 @@ brw_vs_upload_binding_table(struct brw_context *brw)
    const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
    brw_upload_binding_table(brw,
                             _3DSTATE_BINDING_TABLE_POINTERS_VS,
-                            BRW_NEW_VS_BINDING_TABLE, prog_data,
+                            prog_data,
                             &brw->vs.base);
 }
 
@@ -113,6 +116,7 @@ const struct brw_tracked_state brw_vs_binding_table = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP |
              BRW_NEW_VS_CONSTBUF |
              BRW_NEW_VS_PROG_DATA |
              BRW_NEW_SURFACES,
@@ -129,7 +133,7 @@ brw_upload_wm_binding_table(struct brw_context *brw)
    const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
    brw_upload_binding_table(brw,
                             _3DSTATE_BINDING_TABLE_POINTERS_PS,
-                            BRW_NEW_PS_BINDING_TABLE, prog_data,
+                            prog_data,
                             &brw->wm.base);
 }
 
@@ -137,139 +141,97 @@ const struct brw_tracked_state brw_wm_binding_table = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP |
              BRW_NEW_FS_PROG_DATA |
              BRW_NEW_SURFACES,
    },
    .emit = brw_upload_wm_binding_table,
 };
 
-/** Upload the GS binding table (if GS is active). */
+/** Upload the TCS binding table (if tessellation stages are active). */
 static void
-brw_gs_upload_binding_table(struct brw_context *brw)
+brw_tcs_upload_binding_table(struct brw_context *brw)
 {
-   /* If there's no GS, skip changing anything. */
-   if (brw->geometry_program == NULL)
+   /* Skip if the tessellation stages are disabled. */
+   if (brw->programs[MESA_SHADER_TESS_EVAL] == NULL)
       return;
 
-   /* BRW_NEW_GS_PROG_DATA */
-   const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
+   /* BRW_NEW_TCS_PROG_DATA */
+   const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
    brw_upload_binding_table(brw,
-                            _3DSTATE_BINDING_TABLE_POINTERS_GS,
-                            BRW_NEW_GS_BINDING_TABLE, prog_data,
-                            &brw->gs.base);
+                            _3DSTATE_BINDING_TABLE_POINTERS_HS,
+                            prog_data,
+                            &brw->tcs.base);
 }
 
-const struct brw_tracked_state brw_gs_binding_table = {
+const struct brw_tracked_state brw_tcs_binding_table = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_BATCH |
-             BRW_NEW_GS_CONSTBUF |
-             BRW_NEW_GS_PROG_DATA |
-             BRW_NEW_SURFACES,
+             BRW_NEW_BLORP |
+             BRW_NEW_DEFAULT_TESS_LEVELS |
+             BRW_NEW_SURFACES |
+             BRW_NEW_TCS_CONSTBUF |
+             BRW_NEW_TCS_PROG_DATA,
    },
-   .emit = brw_gs_upload_binding_table,
+   .emit = brw_tcs_upload_binding_table,
 };
 
-/**
- * Disable hardware binding table support, falling back to the
- * older software-generated binding table mechanism.
- */
-void
-gen7_disable_hw_binding_tables(struct brw_context *brw)
+/** Upload the TES binding table (if TES is active). */
+static void
+brw_tes_upload_binding_table(struct brw_context *brw)
 {
-   if (!brw->use_resource_streamer)
+   /* If there's no TES, skip changing anything. */
+   if (brw->programs[MESA_SHADER_TESS_EVAL] == NULL)
       return;
-   /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
-    * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
-    *
-    * "When switching between HW and SW binding table generation, SW must
-    * issue a state cache invalidate."
-    */
-   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
-
-   int pkt_len = brw->gen >= 8 ? 4 : 3;
 
-   BEGIN_BATCH(pkt_len);
-   OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
-   if (brw->gen >= 8) {
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-   } else {
-      OUT_BATCH(HSW_BT_POOL_ALLOC_MUST_BE_ONE);
-      OUT_BATCH(0);
-   }
-   ADVANCE_BATCH();
+   /* BRW_NEW_TES_PROG_DATA */
+   const struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data;
+   brw_upload_binding_table(brw,
+                            _3DSTATE_BINDING_TABLE_POINTERS_DS,
+                            prog_data,
+                            &brw->tes.base);
 }
 
-/**
- * Enable hardware binding tables and set up the binding table pool.
- */
-void
-gen7_enable_hw_binding_tables(struct brw_context *brw)
+const struct brw_tracked_state brw_tes_binding_table = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP |
+             BRW_NEW_SURFACES |
+             BRW_NEW_TES_CONSTBUF |
+             BRW_NEW_TES_PROG_DATA,
+   },
+   .emit = brw_tes_upload_binding_table,
+};
+
+/** Upload the GS binding table (if GS is active). */
+static void
+brw_gs_upload_binding_table(struct brw_context *brw)
 {
-   if (!brw->use_resource_streamer)
+   /* If there's no GS, skip changing anything. */
+   if (brw->programs[MESA_SHADER_GEOMETRY] == NULL)
       return;
 
-   if (!brw->hw_bt_pool.bo) {
-      /* We use a single re-usable buffer object for the lifetime of the
-       * context and size it to maximum allowed binding tables that can be
-       * programmed per batch:
-       *
-       * From the Haswell PRM, Volume 7: 3D Media GPGPU,
-       * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
-       * "A maximum of 16,383 Binding tables are allowed in any batch buffer"
-       */
-      static const int max_size = 16383 * 4;
-      brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->bufmgr, "hw_bt",
-                                              max_size, 64);
-      brw->hw_bt_pool.next_offset = 0;
-   }
-
-   /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
-    * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
-    *
-    * "When switching between HW and SW binding table generation, SW must
-    * issue a state cache invalidate."
-    */
-   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
-
-   int pkt_len = brw->gen >= 8 ? 4 : 3;
-   uint32_t dw1 = BRW_HW_BINDING_TABLE_ENABLE;
-   if (brw->is_haswell) {
-      dw1 |= SET_FIELD(GEN7_MOCS_L3, GEN7_HW_BT_POOL_MOCS) |
-             HSW_BT_POOL_ALLOC_MUST_BE_ONE;
-   } else if (brw->gen >= 8) {
-      dw1 |= BDW_MOCS_WB;
-   }
-
-   BEGIN_BATCH(pkt_len);
-   OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
-   if (brw->gen >= 8) {
-      OUT_RELOC64(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
-      OUT_BATCH(brw->hw_bt_pool.bo->size);
-   } else {
-      OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
-      OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0,
-             brw->hw_bt_pool.bo->size);
-   }
-   ADVANCE_BATCH();
-}
-
-void
-gen7_reset_hw_bt_pool_offsets(struct brw_context *brw)
-{
-   brw->hw_bt_pool.next_offset = 0;
+   /* BRW_NEW_GS_PROG_DATA */
+   const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
+   brw_upload_binding_table(brw,
+                            _3DSTATE_BINDING_TABLE_POINTERS_GS,
+                            prog_data,
+                            &brw->gs.base);
 }
 
-const struct brw_tracked_state gen7_hw_binding_tables = {
+const struct brw_tracked_state brw_gs_binding_table = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP |
+             BRW_NEW_GS_CONSTBUF |
+             BRW_NEW_GS_PROG_DATA |
+             BRW_NEW_SURFACES,
    },
-   .emit = gen7_enable_hw_binding_tables
+   .emit = brw_gs_upload_binding_table,
 };
-
 /** @} */
 
 /**
@@ -300,10 +262,9 @@ const struct brw_tracked_state brw_binding_table_pointers = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_BATCH |
-             BRW_NEW_GS_BINDING_TABLE |
-             BRW_NEW_PS_BINDING_TABLE |
-             BRW_NEW_STATE_BASE_ADDRESS |
-             BRW_NEW_VS_BINDING_TABLE,
+             BRW_NEW_BLORP |
+             BRW_NEW_BINDING_TABLE_POINTERS |
+             BRW_NEW_STATE_BASE_ADDRESS,
    },
    .emit = gen4_upload_binding_table_pointers,
 };
@@ -336,10 +297,9 @@ const struct brw_tracked_state gen6_binding_table_pointers = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_BATCH |
-             BRW_NEW_GS_BINDING_TABLE |
-             BRW_NEW_PS_BINDING_TABLE |
-             BRW_NEW_STATE_BASE_ADDRESS |
-             BRW_NEW_VS_BINDING_TABLE,
+             BRW_NEW_BLORP |
+             BRW_NEW_BINDING_TABLE_POINTERS |
+             BRW_NEW_STATE_BASE_ADDRESS,
    },
    .emit = gen6_upload_binding_table_pointers,
 };