i965: Use gen_get_pci_device_id_override

[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp.c

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 38284d3b855401190cc42d06a4d17ab36ef429f2..1d586e5ef38d0e05fe9b40584dbfa4e7cfa8d36c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -106,6 +106,10 @@ brw_blorp_init(struct brw_context *brw)
    case 10:
       brw->blorp.exec = gen10_blorp_exec;
       break;
+   case 11:
+      brw->blorp.exec = gen11_blorp_exec;
+      break;
+
    default:
       unreachable("Invalid gen");
    }
@@ -139,16 +143,17 @@ blorp_surf_for_miptree(struct brw_context *brw,
          intel_miptree_check_level_layer(mt, *level, start_layer + i);
    }
 
-   surf->surf = &mt->surf;
-   surf->addr = (struct blorp_address) {
-      .buffer = mt->bo,
-      .offset = mt->offset,
-      .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
-      .mocs = brw_get_bo_mocs(devinfo, mt->bo),
+   *surf = (struct blorp_surf) {
+      .surf = &mt->surf,
+      .addr = (struct blorp_address) {
+         .buffer = mt->bo,
+         .offset = mt->offset,
+         .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
+         .mocs = brw_get_bo_mocs(devinfo, mt->bo),
+      },
+      .aux_usage = aux_usage,
    };
 
-   surf->aux_usage = aux_usage;
-
    struct isl_surf *aux_surf = NULL;
    if (mt->mcs_buf)
       aux_surf = &mt->mcs_buf->surf;
@@ -319,7 +324,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
    enum isl_format dst_isl_format =
       brw_blorp_to_isl_format(brw, dst_format, true);
    enum isl_aux_usage dst_aux_usage =
-      intel_miptree_render_aux_usage(brw, dst_mt, dst_isl_format, false);
+      intel_miptree_render_aux_usage(brw, dst_mt, dst_isl_format,
+                                     false, false);
    const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
    intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
                                 dst_aux_usage, dst_clear_supported);
@@ -933,7 +939,8 @@ brw_blorp_upload_miptree(struct brw_context *brw,
                                             brw, src_bo, src_format,
                                             src_offset + i * src_image_stride,
                                             width, height, 1,
-                                            src_row_stride, 0);
+                                            src_row_stride,
+                                            ISL_TILING_LINEAR, 0);
 
       if (!src_mt) {
          perf_debug("intel_texsubimage: miptree creation for src failed\n");
@@ -1054,7 +1061,8 @@ brw_blorp_download_miptree(struct brw_context *brw,
                                             brw, dst_bo, dst_format,
                                             dst_offset + i * dst_image_stride,
                                             width, height, 1,
-                                            dst_row_stride, 0);
+                                            dst_row_stride,
+                                            ISL_TILING_LINEAR, 0);
 
       if (!dst_mt) {
          perf_debug("intel_texsubimage: miptree creation for src failed\n");
@@ -1113,7 +1121,7 @@ err:
 
 static bool
 set_write_disables(const struct intel_renderbuffer *irb,
-                   const GLubyte *color_mask, bool *color_write_disable)
+                   const unsigned color_mask, bool *color_write_disable)
 {
    /* Format information in the renderbuffer represents the requirements
     * given by the client. There are cases where the backing miptree uses,
@@ -1127,8 +1135,8 @@ set_write_disables(const struct intel_renderbuffer *irb,
    assert(components > 0);
 
    for (int i = 0; i < components; i++) {
-      color_write_disable[i] = !color_mask[i];
-      disables = disables || !color_mask[i];
+      color_write_disable[i] = !(color_mask & (1 << i));
+      disables = disables || color_write_disable[i];
    }
 
    return disables;
@@ -1165,7 +1173,8 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
    bool can_fast_clear = !partial_clear;
 
    bool color_write_disable[4] = { false, false, false, false };
-   if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
+   if (set_write_disables(irb, GET_COLORMASK(ctx->Color.ColorMask, buf),
+                          color_write_disable))
       can_fast_clear = false;
 
    /* We store clear colors as floats or uints as needed.  If there are
@@ -1264,9 +1273,10 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
           irb->mt, irb->mt_level, irb->mt_layer, num_layers);
 
       enum isl_aux_usage aux_usage =
-         intel_miptree_render_aux_usage(brw, irb->mt, isl_format, false);
+         intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
+                                        false, false);
       intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
-                                   num_layers, isl_format, false);
+                                   num_layers, aux_usage);
 
       struct isl_surf isl_tmp[2];
       struct blorp_surf surf;
@@ -1285,7 +1295,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
       blorp_batch_finish(&batch);
 
       intel_miptree_finish_render(brw, irb->mt, level, irb->mt_layer,
-                                  num_layers, isl_format, false);
+                                  num_layers, aux_usage);
    }
 
    return;
@@ -1443,7 +1453,7 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
 void
 brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
                         unsigned level, unsigned layer,
-                        enum blorp_fast_clear_op resolve_op)
+                        enum isl_aux_op resolve_op)
 {
    DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
 
@@ -1472,7 +1482,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
 
    struct blorp_batch batch;
    blorp_batch_init(&brw->blorp, &batch, brw, 0);
-   blorp_ccs_resolve(&batch, &surf, level, layer,
+   blorp_ccs_resolve(&batch, &surf, level, layer, 1,
                      brw_blorp_to_isl_format(brw, format, true),
                      resolve_op);
    blorp_batch_finish(&batch);
@@ -1519,26 +1529,26 @@ brw_blorp_mcs_partial_resolve(struct brw_context *brw,
 void
 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
                unsigned int level, unsigned int start_layer,
-               unsigned int num_layers, enum blorp_hiz_op op)
+               unsigned int num_layers, enum isl_aux_op op)
 {
    assert(intel_miptree_level_has_hiz(mt, level));
-   assert(op != BLORP_HIZ_OP_NONE);
+   assert(op != ISL_AUX_OP_NONE);
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const char *opname = NULL;
 
    switch (op) {
-   case BLORP_HIZ_OP_DEPTH_RESOLVE:
+   case ISL_AUX_OP_FULL_RESOLVE:
       opname = "depth resolve";
       break;
-   case BLORP_HIZ_OP_HIZ_RESOLVE:
+   case ISL_AUX_OP_AMBIGUATE:
       opname = "hiz ambiguate";
       break;
-   case BLORP_HIZ_OP_DEPTH_CLEAR:
+   case ISL_AUX_OP_FAST_CLEAR:
       opname = "depth clear";
       break;
-   case BLORP_HIZ_OP_NONE:
-      opname = "noop?";
-      break;
+   case ISL_AUX_OP_PARTIAL_RESOLVE:
+   case ISL_AUX_OP_NONE:
+      unreachable("Invalid HiZ op");
    }
 
    DBG("%s %s to mt %p level %d layers %d-%d\n",