brw->blorp.compiler = brw->screen->compiler;
switch (brw->gen) {
+ case 4:
+ if (brw->is_g4x) {
+ brw->blorp.exec = gen45_blorp_exec;
+ } else {
+ brw->blorp.exec = gen4_blorp_exec;
+ }
+ break;
+ case 5:
+ brw->blorp.exec = gen5_blorp_exec;
+ break;
case 6:
brw->blorp.mocs.tex = 0;
brw->blorp.mocs.rb = 0;
brw->blorp.upload_shader = brw_blorp_upload_shader;
}
-static void
-apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
- struct intel_mipmap_tree *mt,
- uint32_t lod,
- uint32_t *offset)
-{
- assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
-
- if (mt->format == MESA_FORMAT_S_UINT8) {
- /* Note: we can't compute the stencil offset using
- * intel_miptree_get_aligned_offset(), because the miptree
- * claims that the region is untiled even though it's W tiled.
- */
- *offset = mt->level[lod].level_y * mt->pitch +
- mt->level[lod].level_x * 64;
- } else {
- *offset = intel_miptree_get_aligned_offset(mt,
- mt->level[lod].level_x,
- mt->level[lod].level_y);
- }
-
- surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
- surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod);
- surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
- surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
- surf->levels = 1;
- surf->array_pitch_el_rows =
- ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
-}
-
static void
blorp_surf_for_miptree(struct brw_context *brw,
struct blorp_surf *surf,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
};
- if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
- mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
- * order to allow for layered rendering. The hack makes each LOD of the
- * stencil or HiZ buffer a single tightly packed array surface at some
- * offset into the surface. Since ISL doesn't know how to deal with the
- * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
- * offset of it anyway, we might as well do the offset here and keep the
- * hacks inside the i965 driver.
- *
- * See also gen6_depth_stencil_state.c
- */
- uint32_t offset;
- apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
- surf->addr.offset += offset;
- *level = 0;
- }
-
struct isl_surf *aux_surf = &tmp_surfs[1];
intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);
/* We only really need a clear color if we also have an auxiliary
* surface. Without one, it does nothing.
*/
- surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
+ surf->clear_color = mt->fast_clear_color;
surf->aux_surf = aux_surf;
surf->aux_addr = (struct blorp_address) {
surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo;
surf->aux_addr.offset = mt->hiz_buf->aux_base.offset;
-
- struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
- if (hiz_mt) {
- assert(brw->gen == 6 &&
- hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
-
- /* gen6 requires the HiZ buffer to be manually offset to the
- * right location. We could fixup the surf but it doesn't
- * matter since most of those fields don't matter.
- */
- apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
- &surf->aux_addr.offset);
- assert(hiz_mt->pitch == aux_surf->row_pitch);
- }
}
} else {
surf->aux_addr = (struct blorp_address) {
}
assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
(surf->aux_addr.buffer == NULL));
+
+ /* ISL wants real levels, not offset ones. */
+ *level -= mt->first_level;
}
static enum isl_format
(dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT))
return false;
+ /* We also can't handle any combined depth-stencil formats because we
+ * have to reinterpret as a color format.
+ */
+ if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
+ _mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
+ return false;
+
do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
filter, mirror_x, mirror_y);
break;
case GL_STENCIL_BUFFER_BIT:
+ /* Blorp doesn't support combined depth stencil which is all we have
+ * prior to gen6.
+ */
+ if (brw->gen < 6)
+ return false;
+
src_irb =
intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
dst_irb =
if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
return false;
- /* BLORP is only supported from Gen6 onwards. */
- if (brw->gen < 6)
- return false;
-
if (_mesa_get_format_base_format(src_rb->Format) !=
_mesa_get_format_base_format(dst_image->TexFormat)) {
return false;
return false;
}
+ /* We also can't handle any combined depth-stencil formats because we
+ * have to reinterpret as a color format.
+ */
+ if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
+ _mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
+ return false;
+
if (!brw->format_supported_as_render_target[dst_image->TexFormat])
return false;
GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
GLbitfield mask, GLenum filter)
{
- /* BLORP is not supported before Gen6. */
- if (brw->gen < 6)
- return mask;
-
static GLbitfield buffer_bits[] = {
GL_COLOR_BUFFER_BIT,
GL_DEPTH_BUFFER_BIT,
can_fast_clear = false;
if (can_fast_clear) {
- union gl_color_union override_color =
+ union isl_color_value clear_color =
brw_meta_convert_fast_clear_color(brw, irb->mt,
&ctx->Color.ClearColor);
- /* Record the clear color in the miptree so that it will be
- * programmed in SURFACE_STATE by later rendering and resolve
- * operations.
- */
- const bool color_updated = brw_meta_set_fast_clear_color(
- brw, &irb->mt->gen9_fast_clear_color,
- &override_color);
-
/* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
* is redundant and can be skipped.
*/
- if (!color_updated && fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
+ if (fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR &&
+ memcmp(&irb->mt->fast_clear_color,
+ &clear_color, sizeof(clear_color)) == 0)
return true;
+ irb->mt->fast_clear_color = clear_color;
+
/* If the MCS buffer hasn't been allocated yet, we need to allocate
* it now.
*/
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_fast_clear(&batch, &surf,
- (enum isl_format)brw->render_target_format[format],
+ brw->render_target_format[format],
level, logical_layer, num_layers,
x0, y0, x1, y1);
blorp_batch_finish(&batch);
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_clear(&batch, &surf,
- (enum isl_format)brw->render_target_format[format],
+ brw->render_target_format[format],
ISL_SWIZZLE_IDENTITY,
level, irb_logical_mt_layer(irb), num_layers,
x0, y0, x1, y1,
PIPE_CONTROL_CS_STALL);
}
-static void
-gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum blorp_hiz_op op)
-{
- assert(intel_miptree_level_has_hiz(mt, level));
-
- struct isl_surf isl_tmp[2];
- struct blorp_surf surf;
- blorp_surf_for_miptree(brw, &surf, mt, true, (1 << ISL_AUX_USAGE_HIZ),
- &level, layer, 1, isl_tmp);
-
- struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw, 0);
- blorp_gen6_hiz_op(&batch, &surf, level, layer, op);
- blorp_batch_finish(&batch);
-}
-
/**
* Perform a HiZ or depth resolve operation.
*
*/
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum blorp_hiz_op op)
+ unsigned int level, unsigned int start_layer,
+ unsigned int num_layers, enum blorp_hiz_op op)
{
const char *opname = NULL;
break;
}
- DBG("%s %s to mt %p level %d layer %d\n",
- __func__, opname, mt, level, layer);
+ DBG("%s %s to mt %p level %d layers %d-%d\n",
+ __func__, opname, mt, level, start_layer, start_layer + num_layers - 1);
+
+ /* The following stalls and flushes are only documented to be required for
+ * HiZ clear operations. However, they also seem to be required for the
+ * HiZ resolve operation which is basically the same as a fast clear only a
+ * different value is written into the HiZ surface.
+ */
+ if (op == BLORP_HIZ_OP_DEPTH_CLEAR || op == BLORP_HIZ_OP_HIZ_RESOLVE) {
+ if (brw->gen == 6) {
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
+ *
+ * "If other rendering operations have preceded this clear, a
+ * PIPE_CONTROL with write cache flush enabled and Z-inhibit
+ * disabled must be issued before the rectangle primitive used for
+ * the depth buffer clear operation.
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ } else if (brw->gen >= 7) {
+ /*
+ * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
+ *
+ * If other rendering operations have preceded this clear, a
+ * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
+ * enabled must be issued before the rectangle primitive used for
+ * the depth buffer clear operation.
+ *
+ * Same applies for Gen8 and Gen9.
+ *
+ * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
+ * PIPE_CONTROL, Depth Cache Flush Enable:
+ *
+ * This bit must not be set when Depth Stall Enable bit is set in
+ * this packet.
+ *
+ * This is confirmed to hold for real, HSW gets immediate gpu hangs.
+ *
+ * Therefore issue two pipe control flushes, one for cache flush and
+ * another for depth stall.
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
+ }
+ }
if (brw->gen >= 8) {
- gen8_hiz_exec(brw, mt, level, layer, op);
+ for (unsigned a = 0; a < num_layers; a++)
+ gen8_hiz_exec(brw, mt, level, start_layer + a, op);
} else {
- gen6_blorp_hiz_exec(brw, mt, level, layer, op);
+ assert(intel_miptree_level_has_hiz(mt, level));
+
+ struct isl_surf isl_tmp[2];
+ struct blorp_surf surf;
+ blorp_surf_for_miptree(brw, &surf, mt, true, (1 << ISL_AUX_USAGE_HIZ),
+ &level, start_layer, num_layers, isl_tmp);
+
+ struct blorp_batch batch;
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
+ blorp_hiz_op(&batch, &surf, level, start_layer, num_layers, op);
+ blorp_batch_finish(&batch);
+ }
+
+
+ /* The following stalls and flushes are only documented to be required for
+ * HiZ clear operations. However, they also seem to be required for the
+ * HiZ resolve operation which is basically the same as a fast clear only a
+ * different value is written into the HiZ surface.
+ */
+ if (op == BLORP_HIZ_OP_DEPTH_CLEAR || op == BLORP_HIZ_OP_HIZ_RESOLVE) {
+ if (brw->gen == 6) {
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
+ *
+ * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
+ * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
+ * and Then followed by Depth FLUSH'
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_DEPTH_STALL);
+
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ }
}
}
projects / mesa.git / blobdiff