key, key_size, kernel_out, prog_data_out);
}
-static void
+static bool
brw_blorp_upload_shader(struct blorp_context *blorp,
const void *key, uint32_t key_size,
const void *kernel, uint32_t kernel_size,
brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
kernel, kernel_size, prog_data, prog_data_size,
kernel_out, prog_data_out);
+ return true;
}
void
brw->blorp.compiler = brw->screen->compiler;
switch (brw->gen) {
+ case 4:
+ if (brw->is_g4x) {
+ brw->blorp.exec = gen45_blorp_exec;
+ } else {
+ brw->blorp.exec = gen4_blorp_exec;
+ }
+ break;
+ case 5:
+ brw->blorp.exec = gen5_blorp_exec;
+ break;
case 6:
brw->blorp.mocs.tex = 0;
brw->blorp.mocs.rb = 0;
}
assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
(surf->aux_addr.buffer == NULL));
+
+ /* ISL wants real levels, not offset ones. */
+ *level -= mt->first_level;
}
static enum isl_format
(dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT))
return false;
+ /* We also can't handle any combined depth-stencil formats because we
+ * have to reinterpret as a color format.
+ */
+ if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
+ _mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
+ return false;
+
do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
filter, mirror_x, mirror_y);
break;
case GL_STENCIL_BUFFER_BIT:
+ /* Blorp doesn't support combined depth stencil which is all we have
+ * prior to gen6.
+ */
+ if (brw->gen < 6)
+ return false;
+
src_irb =
intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
dst_irb =
if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
return false;
- /* BLORP is only supported from Gen6 onwards. */
- if (brw->gen < 6)
- return false;
-
if (_mesa_get_format_base_format(src_rb->Format) !=
_mesa_get_format_base_format(dst_image->TexFormat)) {
return false;
return false;
}
+ /* We also can't handle any combined depth-stencil formats because we
+ * have to reinterpret as a color format.
+ */
+ if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
+ _mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
+ return false;
+
if (!brw->format_supported_as_render_target[dst_image->TexFormat])
return false;
GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
GLbitfield mask, GLenum filter)
{
- /* BLORP is not supported before Gen6. */
- if (brw->gen < 6)
- return mask;
-
static GLbitfield buffer_bits[] = {
GL_COLOR_BUFFER_BIT,
GL_DEPTH_BUFFER_BIT,
DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
irb->mt, irb->mt_level, irb->mt_layer, num_layers);
+ /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
+ *
+ * "Any transition from any value in {Clear, Render, Resolve} to a
+ * different value in {Clear, Render, Resolve} requires end of pipe
+ * synchronization."
+ *
+ * In other words, fast clear ops are not properly synchronized with
+ * other drawing. We need to use a PIPE_CONTROL to ensure that the
+ * contents of the previous draw hit the render target before we resolve
+ * and again afterwards to ensure that the resolve is complete before we
+ * do any more regular drawing.
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_fast_clear(&batch, &surf,
- (enum isl_format)brw->render_target_format[format],
+ brw->render_target_format[format],
level, logical_layer, num_layers,
x0, y0, x1, y1);
blorp_batch_finish(&batch);
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+
/* Now that the fast clear has occurred, put the buffer in
* INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
* redundant clears.
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_clear(&batch, &surf,
- (enum isl_format)brw->render_target_format[format],
+ brw->render_target_format[format],
ISL_SWIZZLE_IDENTITY,
level, irb_logical_mt_layer(irb), num_layers,
x0, y0, x1, y1,
blorp_batch_finish(&batch);
}
- /*
- * Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
- *
- * Any transition from any value in {Clear, Render, Resolve} to a
- * different value in {Clear, Render, Resolve} requires end of pipe
- * synchronization.
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_CS_STALL);
-
return true;
}
resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
}
+ /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
+ *
+ * "Any transition from any value in {Clear, Render, Resolve} to a
+ * different value in {Clear, Render, Resolve} requires end of pipe
+ * synchronization."
+ *
+ * In other words, fast clear ops are not properly synchronized with
+ * other drawing. We need to use a PIPE_CONTROL to ensure that the
+ * contents of the previous draw hit the render target before we resolve
+ * and again afterwards to ensure that the resolve is complete before we
+ * do any more regular drawing.
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+
+
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_ccs_resolve(&batch, &surf, level, layer,
resolve_op);
blorp_batch_finish(&batch);
- /*
- * Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
- *
- * Any transition from any value in {Clear, Render, Resolve} to a
- * different value in {Clear, Render, Resolve} requires end of pipe
- * synchronization.
- */
+ /* See comment above */
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_CS_STALL);
projects / mesa.git / blobdiff